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* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-1/+8
| | | | | | | | | | | | | The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO is probed. However, it assumes that the first GPIO to be probed is in the first GPIO bank. If this is not the case then the init will write to the wrong registers. Fix this. Also add a note that this code is deprecated. We should move to using device tree instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: link: Add board ID GPIOsSimon Glass2016-03-17-0/+2
| | | | | | | | At present the board ID GPIOs are hard-coded. Move them to the device tree so that we can use general SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: link: Move SPD info into the memory controllerSimon Glass2016-03-17-111/+110
| | | | | | | | | | | The SDRAM SPD (Serial Presence Detect) information should be contained with the SDRAM controller. This makes it easier for the controller to access it and removes the need for a separate compatible string. As a first step, move the information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: link: Add required GPIO propertiesSimon Glass2016-03-17-3/+9
| | | | | | | | In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add some more common MSR indexesSimon Glass2016-03-17-20/+43
| | | | | | | | | Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: cpu: Make the vendor table constSimon Glass2016-03-17-1/+1
| | | | | | | This does not need to be modified at run-time, so make it const. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* malloc_simple: Add a little more debuggingSimon Glass2016-03-17-2/+5
| | | | | | | | Output the pointer returned by each call to malloc(). This can be useful when debugging memory problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Correct a few comments and nitsSimon Glass2016-03-17-3/+4
| | | | | | | | Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add functions to update PCI configuration registersSimon Glass2016-03-17-0/+80
| | | | | | | | | It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* gpio: Use const where possibleSimon Glass2016-03-17-10/+10
| | | | | | | | Some functions do not change the struct gpio_desc parameter. Update these to use const so this is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* gpio: Add a function to obtain a GPIO vector valueSimon Glass2016-03-17-0/+30
| | | | | | | | | | We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO is assigned a single bit and can be set high or low on the circuit board. We already have a legacy function for reading these values. Add one that supports driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cpu: Add support for microcode version and CPU IDSimon Glass2016-03-17-0/+12
| | | | | | | | | Some CPUs use microcode and each core can have a different version of microcode loaded. Also some CPUs support the concept of an integer ID used for identification purposes. Add support for these in the CPU uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* video: Allow simple-panel to be used without regulatorsSimon Glass2016-03-17-8/+10
| | | | | | | | | At present simple-panel requires regulator support and will not build without it. But some panels do not have a power supply, or at least not one that can be controlled. Update the implementation to cope with this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* x86: Document how to play with SeaBIOSBin Meng2016-03-17-2/+55
| | | | | | | Boting SeaBIOS is done via U-Boot's bootelf command. Document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Enable ACPI table generation by defaultBin Meng2016-03-17-0/+1
| | | | | | | Now that ACPI is supported on QEMU, enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Support booting SeaBIOSBin Meng2016-03-17-0/+28
| | | | | | | | | | | | | | | SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Implement functions for writing coreboot tableBin Meng2016-03-17-0/+147
| | | | | | | | To prepare generating coreboot table from U-Boot, implement functions to handle the writing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Support writing configuration tables in high areaBin Meng2016-03-17-0/+11
| | | | | | | | | | For those secondary bootloaders like SeaBIOS who want to live in the F segment, which conflicts the configuration table address, now we allow write_tables() to write the configuration tables in high area (malloc'ed memory). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Simplify codes in write_tables()Bin Meng2016-03-17-27/+34
| | | | | | | | Given all table write routines have the same signature, we can simplify the codes by using a function table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-17-6/+5
| | | | | | | | Change the parameter and return value of write_acpi_tables() to u32 to conform with other table write routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Use a macro for ROM table alignmentBin Meng2016-03-17-5/+7
| | | | | | | Define ROM_TABLE_ALIGN instead of using 1024 directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Change to use start/end address pair in write_tables()Bin Meng2016-03-17-6/+12
| | | | | | | | Add a new variable rom_table_start and pass it to ROM table write routines. This reads better than previous single rom_table_end. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Clean up coreboot_tables.hBin Meng2016-03-17-73/+80
| | | | | | | | | Clean up this file a little bit: - Remove inclusion of <linux/compiler.h> - Use tab in the macro definition Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Move sysinfo related to sysinfo.hBin Meng2016-03-17-4/+2
| | | | | | | | coreboot_tables.h should not include sysinfo related stuff. Move those to asm/arch-coreboot/sysinfo.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng2016-03-17-4/+1
| | | | | | | | Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that coreboot table definitions can be used by other x86 builds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spl: arm: Make sure to include all of the u_boot_list entriesTom Rini2016-03-16-15/+9
| | | | | | | | | | | | | | Starting with 96e5b03 we use a linker list for partition table information. However since we use this in SPL we need to make sure that the SPL linker scripts include these as well. While doing this, it's best to simply include all linker lists to future proof ourselves. Cc: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* mvebu: ds414: Move cmd_syno into ds414 directoryTom Rini2016-03-16-8/+4
| | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case as we don't have other common code nor other Synology borads, move the cmd_syno.c file (which claims to be ds414 specific anyways!) into the ds414 directory and only build it for non-SPL builds. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XXTom Rini2016-03-16-1/+7
| | | | | | | | | | On OMAP4 platforms that also need to calculate their DDR settings we are now getting very close to the linker limit size. Since OMAP44XX is only seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we will know that we don't have it for OMAP44XX. Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* lpc32xx: work_92105: Rework MakefileTom Rini2016-03-16-3/+5
| | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case change things so that we only build the right objects for SPL or non-SPL Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Signed-off-by: Tom Rini <trini@konsulko.com>
* cmd: scsi: Group the command portion together, guard with !CONFIG_SPL_BUILDTom Rini2016-03-16-21/+22
| | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case, the SCSI code needs a lot of attention so for now just guard the command portions. Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Only link cmd_ddr3.o on non-SPL buildsTom Rini2016-03-16-1/+2
| | | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case simply move cmd_ddr3.o over to the list with the rest. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Switch to using the poweroff commandTom Rini2016-03-16-29/+30
| | | | | | | | | | Now that we have a standard way to power off the hardware, switch to using that rather than our own command. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Split monitor code / command codeTom Rini2016-03-16-52/+71
| | | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case, we split the code for supporting the monitor out from the code for loading it. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7xx: Enable NFS boot commandAndrew F. Davis2016-03-15-6/+0
| | | | | | | NFS loading works on DRA7 variants, remove the undefinition. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti_armv7_common: env: Add NFS loading support to default enviromentAndrew F. Davis2016-03-15-0/+6
| | | | | | | | | | | NFS loading is similar to net loading except initial files are loaded over NFS instead of TFTP, this removes the need for multiple different protocol servers running on the host and allows the use of a single network file system containing boot related files in their usual in-filesystem directory. Add defaults for this boot style here. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl_nor: fix warning when compiled for 64bit targetMasahiro Yamada2016-03-15-1/+1
| | | | | | | Fix "warning: cast to pointer from integer of different size". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR: Enable SR in Power Management ControlNishanth Menon2016-03-15-3/+3
| | | | | | | | | | | | | | If EMIF is idle for certain amount of DDR cycles, EMIF will put the DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register is programmed. And also before entering suspend-resume ddr needs to be put in self-refresh. Linux kernel does not program this register before entering suspend and relies on u-boot setting. So configuring it in u-boot. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* keystone2: env: Set mmc as default boot for k2g-evmYan Liu2016-03-15-1/+4
| | | | | | | | | | For k2l, k2e and k2hk, ubi is set to default boot in uboot environment settings; while for k2g, mmc should be the default boot. This patch is to set mmc as default for k2g-evm Signed-off-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* keystone2: env: add env script for booting with an initramfs with firmwareMurali Karicheri2016-03-15-3/+17
| | | | | | | | | | | | | | | | | | | | | This patch updates the env script to include a initramfs with firmware loaded and provided to kernel through second argument of bootz command during boot. Defined DEFAULT_FW_INITRAMFS_BOOT_ENV to have all of the required env variables and use it in evm specific config file. The K2 linux drivers for PCIe and NetCP (1G, 10G) requires serdes firmwares. These requires firmware to be available early through the boot process in some cases to satisfy firmware requests from driver. Hence use a small initramfs to provide the same and update boot env to accommodate this in the boot flow. This method is used when rootfs is nfs and ubifs. This fs contains just lib/firmware folder with all required firmware. When rootfs is on initramfs, then the filesystem has the firmware under lib/firmware and this early initramfs is not required and is not used. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* k2g: configs: Add support to save env in MMCLokesh Vutla2016-03-15-0/+6
| | | | | | | | Adding support to save env in MMC on k2g platforms, as it is the preferred peripheral in saving env. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* k2g: env: Allow use of a script and plain text env filesLokesh Vutla2016-03-15-0/+1
| | | | | | | | | For development purposes, it is easier to use the env import command and plain text or script files instead of script-images. So allow u-boot to load env var from a text file or a script file. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti_armv7_common: env: Consolidate support for loading script and text env filesLokesh Vutla2016-03-15-54/+32
| | | | | | | | | Support for loading bootscript and text env file is duplicated in all TI platforms. Add this information to DEFAULT_MMC_TI_ARGS so that it can be reused in all TI platforms. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* am43xx: configs: Enable USB commands for non usb boot alsoMugunthan V N2016-03-15-1/+3
| | | | | | | | | | | With commit aee119bd70b8 ('am43xx_evm: add usb host boot support') usb commands is removed from U-boot second stage and enbaled only on USB boot config. Fixing this by enable USB commands for both USB boot and in second stage u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* am335x: configs: Fix usb ether boot supportLokesh Vutla2016-03-15-1/+3
| | | | | | | | | | | | | CONFIG_SPL_NET_VCI_STRING is available only with BOOTP. So if CMD_DHCP is enabled for SPL in usb ether boot, it will not pass the right vendor name and failing to download the right file. Also all the net CMD_* are not required in SPL builds. So defining these only for non-SPL builds. Reported-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti_armv7_keystone2: env: Remove securedb.key.bin loadCarlos Hernandez2016-03-15-2/+1
| | | | | | | | | securedb.key.bin is not supported so it should not be loaded by default init_ubi command. Signed-off-by: Carlos Hernandez <ceh@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti_armv7_keystone2: env: Update UBIFS image pathsCarlos Hernandez2016-03-15-4/+5
| | | | | | | | | | | UBI images created by OE does not contain boot partition by default, instead kernel and dtb are placed in /boot directory inside rootfs partition. So update env commands to load files from correct location. Signed-off-by: Carlos Hernandez <ceh@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti_armv7_keystone2: configs: add usb mass storage supportMugunthan V N2016-03-15-0/+1
| | | | | | | | | Add USB mass storage support so that kernel can be read from connected usb storage. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* efi_loader: Pass proper device path in on bootAlexander Graf2016-03-15-15/+37
| | | | | | | | | | | | | | | | | EFI payloads can query for the device they were booted from. Because we have a disconnect between loading binaries and running binaries, we passed in a dummy device path so far. Unfortunately that breaks grub2's logic to find its configuration file from the same device it was booted from. This patch adds logic to have the "load" command call into our efi code to set the device path to the one we last loaded a binary from. With this grub2 properly detects where we got booted from and can find its configuration file, even when searching by-partition. Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: Call fdt preparation functionsAlexander Graf2016-03-15-3/+13
| | | | | | | | | | | We have a nice framework around image fils to prepare a device tree for OS execution. That one patches in missing device tree nodes and fixes up the memory range bits. We need to call that one from the EFI boot path too to get all those nice fixups. This patch adds the call. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm: Allow EFI payload code to take exceptionsAlexander Graf2016-03-15-0/+8
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, r9 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
generated by cgit v1.1 at 2024-11-05 23:42:52 +0000