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* spl: move SPL driver entries to driver/MakefileMasahiro Yamada2015-08-18-31/+39
| | | | | | | | | | | | | Just preparing for upcoming cleaning. The board-specific linker script board/vpac270/u-boot-spl.lds has been touched to avoid build error. It does not change the size of spl/u-boot-spl.bin for this board, so it should be OK. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* linux/kconfig.h: add CPP macros useful for per-image config optionsMasahiro Yamada2015-08-18-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous commit introduced a useful macro used in makefiles, in order to reference to different variables (CONFIG_... or CONFIG_SPL_...) depending on the build context. Per-image config option control is a PITA in C sources, too. Here are some macros useful in C/CPP expressions. CONFIG_IS_ENABLED(FOO) can be used as a shorthand for (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_FOO)) || \ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FOO)) For example, it is useful to describe C code as follows, #if CONFIG_IS_ENABLED(OF_CONTROL) (device tree code) #else (board file code) #endif The ifdef conditional above is switched by CONFIG_OF_CONTROL during the U-Boot proper building (CONFIG_SPL_BUILD is not defined), and by CONFIG_SPL_OF_CONTROL during SPL building (CONFIG_SPL_BUILD is defined). The macro can be used in C context as well, so you can also write the equivalent code as follows: if (CONFIG_IS_ENABLED(OF_CONTROL)) { (device tree code) } else { (board file code) } Another useful macro is CONFIG_VALUE(). CONFIG_VALUE(FOO) is expanded into CONFIG_FOO if CONFIG_SPL_BUILD is undefined, and into CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined. You can write as follows: text_base = CONFIG_VALUE(TEXT_BASE); instead of: #ifdef CONFIG_SPL_BUILD text_base = CONFIG_SPL_TEXT_BASE; #else text_base = CONFIG_TEXT_BASE; #endif This commit also adds slight hacking on fixdep so that it can output a correct list of fixed dependencies. If the fixdep finds CONFIG_IS_ENABLED(FOO) in a source file, we want $(wildcard include/config/foo.h) in the U-boot proper building context, while we want $(wildcard include/config/spl/foo.h) in the SPL build context. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* kbuild: add a makefile macro useful with per-image config optionsMasahiro Yamada2015-08-18-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e02ee2548afe ("kconfig: switch to single .config configuration") made the configuration itself pretty simple, instead, we lost the way to systematically enable/disable config options for each image independently. Our current strategy is, put entries into Makefile.spl for options we need separate enabling, or once enable the options globally in Kconfig and then undef them in Makefile.uncmd_spl if we do not want to compile the features for SPL at all. Things are getting really messy. Besides, "ifdef CONFIG_SPL_BUILD" are sprinkled everywhere in makefiles. This commit adds a variable to help describe makefile simpler. $(SPL_) evaluates to "SPL_" during the SPL build, while to an empty string during building U-boot proper. So, you can write obj-$(CONFIG_$(SPL_)FOO) += foo.o instead of ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FOO) += foo.o else obj-$(CONFIG_FOO) += foo.o endif If CONFIG_SPL_FOO does not exist in Kconfig, it is equivalent to ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FOO) += foo.o endif This is the pattern we often see in our current makefiles. To take advantage of this macro, we should prefix SPL_ for the SPL version of the option when we need independent control between U-boot and SPL. With this naming scheme, I hope our makefiles will be much simplified. It means we want to rename existing config options as follows in the long run: CONFIG_SPL_SERIAL_SUPPORT -> CONFIG_SPL_SERIAL CONFIG_SPL_I2C_SUPPORT -> CONFIG_SPL_I2C CONFIG_SPL_GPIO_SUPPORT -> CONFIG_SPL_GPIO CONFIG_SPL_SPI_SUPPORT -> CONFIG_SPL_SPI CONFIG_SPL_DISABLE_OF_CONTROL -> CONFIG_SPL_OF_CONTROL (inverting the logic) Then drivers/Makefile would be re-worked as follows: obj-$(CONFIG_$(SPL_)SERIAL) += serial/ obj-$(CONFIG_$(SPL_)I2C) += i2c/ obj-$(CONFIG_$(SPL_)GPIO) += gpio/ obj-$(CONFIG_$(SPL_)SPI) += spi/ ... Eventually, SPL-specialized entries in Makefile.spl would go away. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* kbuild: fixdep: optimize code slightlyMasahiro Yamada2015-08-18-3/+4
| | | | | | | | | If the target string matches "CONFIG_", move the pointer p forward. This saves several 7-chars adjustments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fs-test.sh: minor fixesStephen Warren2015-08-18-3/+3
| | | | | | | | | | | | - Re-direct stderr into the log files, so any errors U-Boot emits are visible in the logs. This is relevant if the "reset" shell command attempts to report that it's not supported on the sandbox board. - Fix test_fs_nonfs() to name the files it created differently for each invocation. Otherwise, the logs from different tests overwrite each-other. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Suriyan Ramasami <suriyan.r@gmail.com>
* i2c: lpc32xx: correct sanity check for requested bus speedVladimir Zapolskiy2015-08-18-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit wide. This means that if HCLK is 104MHz, then minimal configurable I2C clock speed is about 51KHz. Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in assumption that peripheral clock is 13MHz it allows to set the minimal bus speed about 25.5KHz. Check for negative half clock value is removed since it is always false. The change fixes the following problem for I2C busses 0 and 1: => i2c dev 0 Setting bus to 0 => i2c speed 100000 Setting bus speed to 100000 Hz Failure changing bus speed (-22) Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* lpc32xx: add common USB OHCI defines for all LPC32xx boardsVladimir Zapolskiy2015-08-18-0/+9
| | | | | | | | The change adds a number of macro definitions used by USB OHCI driver, if CONFIG_USB_OHCI_LPC32XX is selected from a board config file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* usb: lpc32xx: add host USB driverSylvain Lemieux2015-08-18-0/+251
| | | | | | | | | | | | | Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* i2c: lpc32xx: add support for OTG I2CSylvain Lemieux2015-08-18-3/+17
| | | | | | | | Updated the LPC32xx I2C driver to support the OTG I2C that is part of the USB module. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de>
* nand: lpc32xx: add ECC layout for small page NANDSylvain Lemieux2015-08-18-1/+17
| | | | | | | | | | Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (ECC layout for small page) This layout is matching the lpc32xx NAND SLC Linux Kernel driver. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* nand: lpc32xx: add hardware ECC supportSylvain Lemieux2015-08-18-4/+409
| | | | | | | | | | | | Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: move common SLC NAND defines to arch/config.hVladimir Zapolskiy2015-08-18-11/+32
| | | | | | | | | | | | | | | A number of LPC32xx SLC NAND defines is dictated by controller hardware limits and OOB layout is defined by operating system, the definitions are common for all users. Since those macro are used in out of NAND SLC driver code (simple NAND SPL framework), they can not be placed into the driver, therefore move them from board config files to arch/config.h The change also adds OOB layout details specific to small page NAND devices taken from Linux kernel. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* dma: lpc32xx: add DMA driverSylvain Lemieux2015-08-18-0/+226
| | | | | | | | | | | | | Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-08-18-10/+349
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| * ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspiVignesh R2015-08-17-0/+7
| | | | | | | | | | | | | | | | | | | | | | Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode Also add EDMA3 base address for DRA7XX and AM57XX. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * spi: ti_qspi: Use DMA to read from qspi flashVignesh R2015-08-17-0/+25
| | | | | | | | | | | | | | | | ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * dma: ti-edma3: Add helper function to support edma3 transferVignesh R2015-08-17-0/+80
| | | | | | | | | | Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sf: ops: Add spi_flash_copy_mmap functionTom Rini2015-08-17-1/+10
| | | | | | | | | | | | | | | | | | | | When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: AM43XX: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+36
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+52
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+57
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: AM43xx: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+53
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * env: use cache line aligned memory for flash readRavi Babu2015-08-17-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * sf: allocate cache aligned buffers to copy from flashRavi Babu2015-08-17-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * ti: qspi: set flash quad bit based on quad support flagvishalm@ti.com2015-08-17-1/+1
| | | | | | | | | | | | | | | | Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sf: Make 4K sector support configurableMarek Vasut2015-08-17-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the support for 4K subpage I/O on a SPI NOR flash configurable. A board which requires the SPI NOR to be accessed in larger 32KiB or 64KiB pages can disable the 4K subpage support, but by default, the support for 4K subpage I/O is enabled. The functionality of this option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux. This is extremely useful in case one uses UBI on a SPI NOR flash. UBI needs at least 15k EBs and can not work on a flash which uses 4k ones, so disabling the support for 4k subpages lets UBI work on such flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-08-18-8/+6
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| * | ARM: exynos: fix regression for Origen4210Thomas Abraham2015-08-17-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The do_lowlevel_init() function includes certian CA15 specific L2 cache configuration which is only applicable on Exynos5420 and members of its family. Fix the regression on Origen4210 by skipping the Exynos5420 specific portions of the code. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: exynos: move SoC sources to mach-exynosThomas Abraham2015-08-17-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Prepare v2015.10-rc2Tom Rini2015-08-17-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-08-17-56/+855
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| * | arm: mvebu: db-88f6820-gp: Enable PCI supportStefan Roese2015-08-17-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x eval board. It also enabled the Intel E1000 driver support and adds the initialization of PCIe network controllers to the board code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
| * | arm: mvebu: db-mv784mp-gp: Enable PCI supportStefan Roese2015-08-17-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP eval board. It also enabled the Intel E1000 driver support and adds the initialization of PCIe network controllers to the board code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | pci: mvebu: Add PCIe driverAnton Schubert2015-08-17-8/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
| * | arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-17-8/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()Stefan Roese2015-08-17-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework these functions so that dram_init_banksize() does not call dram_init() again. It only needs to set the banksize values in the bdinfo struct. Make sure to also clip the size of the last bank if it exceeds the maximum allowed value of 3 GiB (0xc000.0000). Otherwise other address windows (e.g. PCIe) will overlap with this memory window. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Move CONFIG_SYS_TEXT_BASE to an address < 16 MiBStefan Roese2015-08-17-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada XP / 38x boards in mainline U-Boot. This is done in preparation for the ECC SDRAM scrubbing that needs to be done in the main U-Boot. The SPL (previously bin_hdr) has already scrubbed the area: 0x0000.0000 - 0x0100.0000 In this area this main U-Boot needs to get loaded. The main U-Boot then can scrub the remaining SDRAM area while running from this location. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Display ECC enabled / disabled upon bootupStefan Roese2015-08-17-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM bootup text. Making it easier for board with SPD DIMM's to see, if ECC is enabled or not. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: add multiple usb-hostcontroller support for AXPAnton Schubert2015-08-17-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for multiple hostcontrollers to the ehci-marvell driver and enables all 3 usb-hcs on the db-mv784mp-gp board. It depends on the initial Armada XP usb support patch from Stefan. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-mv785mp-gp: Add USB/EHCI supportStefan Roese2015-08-17-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enabled the USB/EHCI support for the Marvell DB-MV784MP-GP Armada XP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Enable USB EHCI support on Armada XPStefan Roese2015-08-17-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU. Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Enable NAND controller on MVEBU SoC'sStefan Roese2015-08-17-7/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Disable MBUS error propagationStefan Roese2015-08-17-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Flush caches and disable MMU only on A38xStefan Roese2015-08-17-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. So to fully release / unlock this area from cache, we need to first flush all caches, then disable the MMU and disable the L2 cache. On Armada XP this does not seem to be needed. Even worse, with this code added, I sometimes see strange input charactes loss from the console. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Setup the MBUS bridge registersStefan Roese2015-08-17-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch, the MBUS bridge registers (base and size) are configured upon each call to mbus_dt_setup_win(). This is needed, since the board code can also call this function in later boot stages. As done in the maxbcm board. This is needed to fix a problem with the secondary CPU's not booting in Linux on AXP. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Change MBUS base addresses and sizesStefan Roese2015-08-17-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the MBUS base addresses and sizes to use more generic names and also adds defines for the sizes. It also moves the base address to higher addresses. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-mv784mp-gp.h: Fix image creation - use correct offsetStefan Roese2015-08-17-0/+1
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on the DB-MV784MP-GP eval board. To really enable ECC support on this board the I2C EEPROM needs to get changed. As it saves the enabling of ECC support internally. For this the following commands can be used to enable ECC support on this board: Its recommended for first save (print) the value(s) in this EEPROM address: => i2c md 4e 0.1 2 0000: 05 00 .. To enable ECC support you need to set bit 1 in the 2nd byte: Marvell>> i2c mw 4e 1.1 02 Marvell>> i2c md 4e 0.1 2 0000: 05 02 .. To disable ECC support again, please use this command: Marvell>> i2c mw 4e 1.1 00 Marvell>> i2c md 4e 0.1 2 0000: 05 00 .. On other AXP boards, simply plugging an ECC DIMM should be enough to enable ECC support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INITStefan Roese2015-08-17-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid of all references here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | Revert "Align global_data to a 16-byte boundary"Simon Glass2015-08-17-3/+1
|/ / | | | | | | | | | | | | | | | | | | This causes widespread breakage due to the operation of the low-level code in crt0.S and cro0_64.S for ARM at least. The fix is not complicated but it seems safer to revert this for now. This reverts commit 2afddae07523f23f77acd066ad1719f53d289f98. Signed-off-by: Simon Glass <sjg@chromium.org>
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