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| | * armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+1106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
| | * armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu2015-10-29-0/+1224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-526/+713
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net/fm: fix MDIO controller base on FMAN2Shaohui Xie2015-10-29-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two FMANs, so we should only define MDIO controller base on FMAN2 when there is FMAN2. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net/fm: Add QSGMII PCS initShaohui Xie2015-10-29-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII PCS needed to be programmed same as SGMII PCS, and there are four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared port 0's MDIO controller, so when programming port 0, we continue to program other three ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net: Move some header files to include/Shaohui Xie2015-10-29-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net: fm: bug fix when CONFIG_PHYLIB not definedShaohui Xie2015-10-29-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | codes related to phylib operations should be wrapped by CONFIG_PHYLIB. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net/fm: Make the return value logic consistent with conventionHou Zhiqiang2015-10-29-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In convention, the '0' is a normal return value indicating there isn't an error. While some functions of FMan IM driver treat '0' as an error return value. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net/fm: Add support for 64-bit platformsHou Zhiqiang2015-10-29-33/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FMan IM driver is developed for 32-bit platfroms and isn't friendly to 64-bit platforms, so do the minimal refactor: 1. Refine the MURAM management and access. 2. Correct the initialization and operations for QDs and BDs. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net/fm: Fix the endian issue to support both endianness platformsHou Zhiqiang2015-10-29-38/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager(FMan) is a big-endian peripheral, so the registers, internal MURAM and BDs, which are allocated in main memory and used to communication between core and FMan, should be accessed in big-endian. The big-endian platforms can access them directly as the code implemented so far, while for the little-endian platforms it need to swap the byte-order. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-29-213/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * common/board_f.c: change the macro name and remove it for PPC platformsGong Qianyu2015-10-29-41/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For most PPC platforms, they will call the first get_clocks() in init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is then defined to call the second get_clocks(), which should be redundant for PPC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * arm: ls102xa: enable snooping for CAAM transactionshoria.geanta@freescale.com2015-10-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv8: ls2085a: Add support of random MAC addressPrabhakar Kushwaha2015-10-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add support of setting RANDOM MAC address if env variable not available. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * driver: net: ldpaa_eth: Set MAC address during interface openPrabhakar Kushwaha2015-10-29-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently ldpaa ethernet driver rely on DPL file to statically configure mac address for the DPNIs. It is not a correct approach. Add support setting MAC address from env variable or Random MAC address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv8: ls2085ardb: enable CONFIG_PHY_AQUANTIAShaohui Xie2015-10-29-0/+1
| | | | | | | | | | | | | | | | | | | | | To support on board Aquantia's PHY AQR405. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * crypto/fsl: SEC driver cleanup for 64 bit and endiannessAneesh Bansal2015-10-29-24/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * Data types defined for 64 bit physical addressAneesh Bansal2015-10-29-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | Data types and I/O functions have been defined for 64 bit physical addresses in arm. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * Pointers in ESBC header made 32 bitAneesh Bansal2015-10-29-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * ls102xa: fdt: Disable IFC in SD boot for QSPIAlison Wang2015-10-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * arm: ls1021a: Add QSPI or IFC support in SD bootAlison Wang2015-10-26-26/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * QE: modify the address of qe ucodeZhao Qiang2015-10-26-2/+2
| | | | | | | | | | | | | | | | | | | | | The address of uboot changed, so change qe ucode Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may ↵Alison Wang2015-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * fdt_support: Don't panic if stdout alias is missingScott Wood2015-10-26-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, using fdt_fixup_stdout() on a device tree that is missing the relevant alias results in this: WARNING: could not set linux,stdout-path FDT_ERR_NOTFOUND. ERROR: /chosen node create failed - must RESET the board to recover. FDT creation failed! hanging...### ERROR ### Please RESET the board ### There is no reason for this to be a fatal error rather than a warning, and removing this allows for a smooth transition on a platform where the device tree currently lacks the correct aliases but will have them in the future. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
| | * arm/fsl-ls: Add CONFIG_OF_STDOUT_VIA_ALIASScott Wood2015-10-26-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This will allow OF-based earlycon to be used once the appropriate aliases are added to the device tree and kernel support is fixed. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | README.scrapyard: Populate recent ppc4xx removalsTom Rini2015-10-30-4/+4
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | | mx7dsabresd: add secure boot supportAdrian Alonso2015-10-30-0/+11
| | | | | | | | | | | | | | | | | | Add secure boot support for mx7dsabresd target board Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: hab: add mx7 secure boot supportAdrian Alonso2015-10-30-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT to get the corresponding bit mask per SoC (mx7 or mx6) to identify if securue boot feature is enabled/disabled. On authenticate_image only check for mmu enabled on mx6 SoC to force pu_irom_mmu_enabled so ROM code can perform mmu cache flush mx7 SoC ROM code does not have this issue as ROM enables cache support based on fuse settings. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: hab: use read_fuse for secure boot settingsAdrian Alonso2015-10-30-5/+12
| | | | | | | | | | | | | | | | | | | | | Use read_fuse api fuction call to read secure boot fuse settings (enabled/disabled). Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | arm: imx: add secure boot fuse details for imx7 SoCAdrian Alonso2015-10-30-0/+8
| | | | | | | | | | | | | | | | | | | | | Add secure boot fuse details (location) bank = 1, word = 3; for imx7 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | arm: imx: add secure boot fuse details for imx6 SoCAdrian Alonso2015-10-30-0/+8
| | | | | | | | | | | | | | | | | | | | | Add secure boot fuse details (location) bank = 0, word = 6; for imx6 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: hab: add secure boot fuse detailsAdrian Alonso2015-10-30-0/+9
| | | | | | | | | | | | | | | | | | | | | Add secure boot fuse helper struct to abstract the way to find out secure boot settings per SoC iMX family Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: hab: rework unified rom section for mx7Adrian Alonso2015-10-30-1/+2
| | | | | | | | | | | | | | | | | | | | | Rework unified section macro select via Kconfig option instead of macro definition in mx7_common header file. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: hab: use unified rom section for mx6sx and mx6ulAdrian Alonso2015-10-30-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target platforms to resolve corresponding HAB_RVT_BASE base address, the RVT table contains pointers to the HAB API functions in ROM code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: hab: rework secure boot support for imx6Adrian Alonso2015-10-30-2/+2
| | | | | | | | | | | | | | | | | | | | | Rework secure boot support for imx6, move existing hab support for imx6 into imx-common for SoC reuse. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: cpu: move common chip revision id'sAdrian Alonso2015-10-30-19/+13
| | | | | | | | | | | | | | | | | | | | | Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | | imx: mx6sabresd: add i.MX6DQP Sabresd supportPeng Fan2015-10-30-6/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6DQP-Sabresd board support: 1. set fdt_file according to board_rev which is set at runtime. 2. Add mx6dqp_ddr_ioregs and calibration value for this board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | | imx: mx6sabresd discard PHYS_SDRAM_SIZEPeng Fan2015-10-30-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This macro is not needed, since gd->ram_size is assigned value using function imx_ddr_size(). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | imx35, flea3: add FIT image supportHeiko Schocher2015-10-30-0/+4
| | | | | | | | | | | | | | | | | | add FIT image support for the flea3 board. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | ts4800: add CONFIG_OF_LIBFDTDamien Riegel2015-10-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Linux only boots IMX.51-based boards with device tree, so this board would benefit from supporting it. Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
* | | arm, imx6, aristainetos2: set gpr register after resetHeiko Schocher2015-10-30-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | setting the gpr 1,8 and 12 registers to a fix value. This is needed because after a WDT reset, this registers are not correct resettet, and prevent linux from booting again. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | arm, imx: add some gpr register definesHeiko Schocher2015-10-30-0/+35
| | | | | | | | | | | | | | | | | | add some missing gpr register defines. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | driver: misc: add MXC_OCOTP Kconfig entryPeng Fan2015-10-30-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add MXC_OCOTP Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | | imx-common: timer: clean up codePeng Fan2015-10-30-73/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can reuse common functions in lib/time.c, but not reimplement functions in imx-common/time.c. Only keep timer_init ,get_tbclk and implement timer_read_counter in imx-common/time.c. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-10-30-10293/+7187
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| * | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-10-29-114/+326
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| | * | net: eth: Check return value in various placesBin Meng2015-10-29-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eth_get_dev() can return NULL which means device_probe() fails for that ethernet device. Add return value check in various places or U-Boot will crash due to NULL pointer access. With this commit, 'dm_test_eth_act' test case passes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | dm: test: Add a new test case against dm eth codes for NULL pointer accessBin Meng2015-10-29-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashes when doing a 'ping' with the following test scenario: - All ethernet devices are not probed - "ethaddr" for all ethernet devices are not set - "ethact" is set to a valid ethernet device name Add a new test case 'dm_test_eth_act' to hit such scenario. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | net: eth: Clear MAC address in eth_pre_remove()Bin Meng2015-10-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platdata->enetaddr was assigned to a value in dev_probe() last time. If we don't clear it, for dev_probe() at the second time, dm eth will end up treating it as a MAC address from ROM no matter where it came from originally (maybe env, ROM, or even random). Fix this by clearing platdata->enetaddr when removing an Ethernet device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
generated by cgit v1.1 at 2024-10-22 11:31:27 +0000