summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
...
* MLK-13440-5 fsl_usdhc: Remove the CONFIG_SYS_FSL_ESDHC_FORCE_VSELECTYe Li2016-11-08-4/+0
| | | | | | | | | Since we have added the "vs18_enable" parameter for fixed 1.8v I/O, remove the CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT. This configuration can only work with one MMC device. If more devices are supported, this will set 1.8v to all controllers, so will cause problem to 3.3v devices. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13440-4 warp: Replace CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT by using ↵Ye Li2016-11-08-2/+1
| | | | | | | | | vs18_enable parameter Change to use the new way to set the vs18_enable field to 1 for fixed 1.8v I/O eMMC. Don't use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT any longer. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13440-3 mx6sll_arm2: Update USDHC2 parameter for using 1.8V I/OYe Li2016-11-08-6/+2
| | | | | | | | Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC. Also remove the explicit USDCH2 vendorspec register settings in board codes, since the driver will take charge of it. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13440-2 mx6sllevk: Update USDHC2 parameter for using 1.8V I/OYe Li2016-11-08-6/+2
| | | | | | | | Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC. Also remove the explicit USDCH2 vendorspec register settings in board codes, since the driver will take charge of it. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13440-1: fsl_usdhc: Add configuration parameter for using fixed 1.8V I/OYe Li2016-11-08-0/+6
| | | | | | | | | | | | | | When using eMMC with 1.8V I/O, we have to set the VSELECT bit at this USDHC controller setup and init. The CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT has problem that it will apply to all USDHC controllers and it only set the 1.8V at init phase. So if user does not select to the eMMC device, the voltage on the I/O pins are not correct. This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg structure, so each controller can have different settings. The default value is 0 for 3.3V, which is compatible with current codes. When setting this value to 1, at USDHC setup and init phase the driver will set the VSELECT bit. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13405-4 mx6sll-arm2: change the eMMC reset pad to 1.8vHaibo Chen2016-11-04-2/+6
| | | | | | | | | | eMMC is connected fixed to 1.8v, so need to set the LVE of pad sd2_rst. Also need to set the VSELECT to change all the eMMC pad (cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and SD3 voltage switch. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-13405-3 mx6sll-evk: change the eMMC reset pad to 1.8vHaibo Chen2016-11-04-2/+6
| | | | | | | | | | eMMC is connected fixed to 1.8v, so need to set the LVE of pad sd2_rst. Also need to set the VSELECT to change all the eMMC pad (cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and SD3 voltage switch. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-13410 Android: Change to set mfgtool only for none android u-bootYe Li2016-11-02-2/+2
| | | | | | | | | | The mfgtool environments only can set in BSP u-boot image, not for android u-boot. Since android u-boot may go into fastboot in board_r phase which is earlier than mfgtool environment check. The USB status from android fastboot will cause u-boot to configure mfgtool environment. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 066f001a19bdc51b0fc0d65bcb87081b01f957c2)
* MLK-13407: mx6qarm2: mt128x64mx3 2: add init pre charge all commandAdrian Alonso2016-10-31-3/+10
| | | | | | | | | | | | | - Adjust ZQ delay for MMDC clock frequency at 400MHz - Precharge all commands per JEDEC The memory controller may optionally issue a Precharge-All command prior to the MRW Reset command, this is strongly recommended to ensure a robust DRAM initialization DDR Calibration script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/a72e010a1fd8c7fe0fda7bdc4d058c478e94c3da Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13292 mx6sxscm: evb: add support for epop evb boardAlejandro Sierra2016-10-26-0/+5
| | | | | | | | | Support for the ePOP i.MX SX SCM Evaluation Board (EVB) This provides the configuration files for 512mb and emmc support. Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13290 mx6sxscm: evb: add support for 1gb evb boardAlejandro Sierra2016-10-26-0/+15
| | | | | | | | | | | | Support for the i.MX SX SCM Evaluation Board (EVB) Providing configuration files for - Regular 1gb board - m4fastup configuration - qspi2 support Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13289 imx: mx6sxscm: generic mx6sxscm board supportJuan Gutierrez2016-10-26-0/+1435
| | | | | | | | | | | | | | Provide the generic support for i.MX6SX SCM boards i.MX6SX SCM board file with the generic configuration, LPDDR2 memory calibration and build support is provided. - LPDDR2 memory configuration files for 1GB and 512MB. - plugin support for the above configurations. - driver support for: uart, qspi, i2c, usb, mmc. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13392 configs: add extra misc NAND partition for AndroidHan Xu2016-10-26-25/+25
| | | | | | | add one more extra NAND partition in u-boot environment setting to support Android. Signed-off-by: Han Xu <han.xu@nxp.com>
* MLK-13258 mx6dqscm: evb: support for 1Gb SCM EVB boardJuan Gutierrez2016-10-21-0/+10
| | | | | | | | | Support for the 1GB SCM Evaluation board (EVB) 2 defconfig files are provided for EVB: Android and SD Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13256 mx6dqscm: qwks: add support for 1Gb SCM QWKS boardJuan Gutierrez2016-10-21-0/+15
| | | | | | | | | | | | Support for the 1GB SCM Quick Start board (QWKS) - 3 defconfig files are provided for QWKS: Android, Regular SD and SPI-NOR - SD and or SPI-NOR boot are supported on fix mode. - Due to performance, interleave is the default mode for Android. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13255 imx: mx6dqscm: generic mx6dqscm board supportJuan Gutierrez2016-10-21-0/+3161
| | | | | | | | | | | | | Provide the generic support for i.MX6DQ SCM boards - LPDDR2 memory configuration files for 1GB, 2GB and 512MB. - plugin support for the above configurations. - fix and interleave memory mode (selected by CONFIG option) - driver support for: uart, spi, i2c, usb, sata and fec. - Android support Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13373 mx6sll: update ddr script to 2.1.1Peng Fan2016-10-21-4/+4
| | | | | | | | | | | | | | | | Update ddr script to 2.1.1 Script: http://compass.freescale.net/livelink/livelink/235732623/EVK_IMX6SLL_LPDDR3_400MHz_512MB_32bit_V2.1.1.txt?func=doc.Fetch&nodeid=235732623 Version 2.1.1: -Update [MMDC_MPRDDLCTL] and [MMDC_MPWRDLCTL] based on calibration results -setmem /32 0x021B0848 = 0x3F393B3C // [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register -setmem /32 0x021B0850 = 0x262C3826 // [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration Register Tested on two boards. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13352 imx: mx6sll: support mx6sllevk boardPeng Fan2016-10-19-0/+1043
| | | | | | | | | | Add mx6sll evk board support. USB/LCDIF/I2C/SD/EMMC/WDOG supported. The ddr script is from mx6sll lpddr3 arm2 board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13360 mx6sll_arm2: Fix typo issue in mx6sll LPDDR2 ARM2 defconfigYe Li2016-10-18-1/+1
| | | | | | Change the 'kONFIG' to 'CONFIG', otherwise will get build warning: unexpected data Signed-off-by: Ye Li <ye.li@nxp.com>
* mmc: sd: optimize erasePeng Fan2016-10-18-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | To SD, there is no erase group, then the value erase_grp_size will be default 1. When erasing SD blocks, the blocks will be erased one by one, which is time consuming. We use AU_SIZE as a group to speed up the erasing. Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB. `time mmc erase 0x100000 0x2000` time: 44.856 seconds (before optimization) time: 0.335 seconds (after optimization) Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com> (cherry picked from commit e492dbb41e025ac1a7d7934b1df52b2f0485f8dd)
* mmc: sd: extracting erase related information from sd statusPeng Fan2016-10-18-0/+77
| | | | | | | | | | | | | | | | | Add function to read SD_STATUS information. According to the information, get erase_timeout/erase_size/erase_offset. Add a structure sd_ssr to include the erase related information. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com> (cherry picked from commit 3697e5992f89c923aca17d7d9174739da28cb3cd)
* MLK-13336 mx6sll_arm2: Update LPDDR2 script to v2.1Ye Li2016-10-13-3/+10
| | | | | | | | | | | | | | | | | | | | Changes: Version 2.1 -Issue a Precharge-All command prior to the MRW Reset command. setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results setmem /32 0x021B0848 = 0x3A383C40 // [MMDC_MPRDDLCTL] setmem /32 0x021B0850 = 0x242C3020 // [MMDC_MPWRDLCTL] File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Passed overnight memtester on one i.MX6SLL LPDDR2 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13335 mx6sl: Fix build break for all i.MX6SL boardsYe Li2016-10-13-2/+2
| | | | | | | | Since the UART1 register base name is changed from UART1_IPS_BASE_ADDR to UART1_BASE to align with other i.MX6 chips. Should update the board configuration header file with the new name. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13331 mx6sll_arm2: Output WDOG_B signal to reset PMICYe Li2016-10-12-0/+8
| | | | | | | Since the LPDDR2/3 does not have reset pin, to keep safe reset, we need to use WDOG_B to reset PMIC. Add pinmux and relevant settings. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13330 mx6sll_arm2: Update LPDDR3 script to v2.2Ye Li2016-10-12-7/+14
| | | | | | | | | | | | | | | | | | | | | | | Changes from v1.2 to v2.2: Version 2.2 -Issue a Precharge-All command prior to the MRW Reset command. -setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 -setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 Version 2.1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results -setmem /32 0x021B0848 = 0x3C3A3C3C // [MMDC_MPRDDLCTL] -setmem /32 0x021B0850 = 0x24293625 // [MMDC_MPWRDLCTL] Version 1.2.1 -Fix a typo. setmem /32 0x020E052C = 0x00000030 -Fix a typo. setmem /32 0x021B0800 = 0xA1390003 File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Overnight memtester passed on two i.MX6SLL LPDDR3 ARM2 boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13311 configs: mx6sll_lpddr3_arm2: Enable network functionPeter Chen2016-10-11-0/+5
| | | | | | | Since mx6sll has no ethernet controller, we take USB ethernet device as network device by default. Signed-off-by: Peter Chen <peter.chen@nxp.com>
* MLK-13307-15 imx: mx6sll: add mx6sll arm2 supportPeng Fan2016-10-11-0/+1352
| | | | | | | | | | | Add mx6sll lpddr3/lpddr2 arm2 support. LCDIF/SPI/USB/PMIC supported. LPDDR3 DDR version: 1.2 LPDDR2 DDR version: initial version. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-14 imx-common: lcdif: update lcdif regs for i.MX6SLLPeng Fan2016-10-11-4/+5
| | | | | | | Update lcdif regs for i.MX6SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-13 OCOTP: Update OCOTP driver to support i.MX6SLLYe Li2016-10-11-8/+10
| | | | | | | | The i.MX6SLL reuses the i.MX6ULL fuse, and has same fuse bank map. Add the i.MX6SLL support to OCOTP driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2016-10-11-6/+71
| | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-11 imx: mx6sll: disable LDOPeng Fan2016-10-11-0/+2
| | | | | | There is no LDO for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-10 mx6_common: correct loadaddr and text base for i.MX6SLLPeng Fan2016-10-11-1/+1
| | | | | | Correct loadaddr and text base for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-9 imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-10-11-0/+4
| | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-8 imx-common: cache: configure L2 Cache for i.MX6SLLPeng Fan2016-10-11-1/+1
| | | | | | Configure L2 Cache for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2016-10-11-5/+16
| | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-6 imx: mx6sll: add clock support for i.MX6SLLPeng Fan2016-10-11-36/+158
| | | | | | | Update clock settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-5 imx: mx6sll: add iomux settingsPeng Fan2016-10-11-4/+10
| | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-4 imx-common: timer: add i.MX6SLL supportPeng Fan2016-10-11-2/+4
| | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-3 imx: mx6sll: update register addressPeng Fan2016-10-11-41/+52
| | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-2 imx: mx6sll: add pinmux header filesPeng Fan2016-10-11-0/+1021
| | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-1 imx: Add MX6SLL CPU typePeng Fan2016-10-11-1/+4
| | | | | | | Add i.MX6SLL CPU type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mx6: clock: Fix the logic for reading axi_alt_selFabio Estevam2016-09-18-2/+2
| | | | | | | | | | | | | | According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> (cherry picked from commit 8f2e2f15ffa1bb03b6e6e189312426059f3215d1)
* MLK-13131: mx6qarm2: add fastboot and recovery supportAdrian Alonso2016-09-13-0/+33
| | | | | | Add fastboot and recovery mode support for mx6qarm Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13130: configs: mx6qarm2: android lpddr2 pop supportAdrian Alonso2016-09-13-1/+94
| | | | | | Add Android support for mx6qarm2 lpddr2 pop target Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividersAdrian Alonso2016-09-07-1/+1
| | | | | | | | Adjust ahb/axi clock root podf dividers to be divided by 1 to allow ahb/axi clock root to be 24Mhz when sourced from osc_clk. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* Disable MMU and Cache when using pluginUtkarsh Gupta2016-09-01-0/+28
| | | | Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
* MLK-13141 mx6qpsabresd: Do not touch VGEN3 and VGEN5Robin Gong2016-08-30-12/+14
| | | | | | | | VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board, so software didn't need to change their voltage output anymore. Otherwise, VGEN3 will be wrongly updated from 1.8v to 2.8v. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-13140 ARM: imx: update REFTOP_VBGADJ according to fuse settingBai Ping2016-08-30-5/+0
| | | | | | | | | | | | | | | | On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13124 ARM: imx: update the REFTOP_VBGADJ settingBai Ping2016-08-25-6/+32
| | | | | | | | | | | | | | | | | Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13115 imx: mx6ullevk: Update LPDDR2 script for i.MX6ULL 9x9 EVKYe Li2016-08-23-4/+4
| | | | | | | | | | | | | | | | | | Update the LPDDR2 script to 1.2 rev with delay line settings changed. File: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx Changes: Update Delay Line Settings based on the delay line calibration results of more boards. MMDC_MPRDDLCTL = 0x40403439 MMDC_MPWRDLCTL = 0X4040342D Test: One 9x9 EVK board pass stress memtester. Signed-off-by: Ye Li <ye.li@nxp.com>
generated by cgit v1.1 at 2024-11-26 21:24:33 +0000