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* ARM: tegra: pull Tegra30 SoC DT from Linux v4.7Stephen Warren2016-09-27-144/+783
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Modification of PCIe memory region addresses. The HW memory layout is programmable, so this should work fine, and Beaver PCIe was tested without issue. * Removal of pcie_xclk from the PCIe node and clock binding header. This clock doesn't exist and isn't used; only a reset with this ID exists. * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Changed the phy_type value for the second USB port. This required board DTs to be updated to keep the same configuration. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra30-mc.h since tegra30.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * None. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pull Tegra20 SoC DT from Linux v4.7Stephen Warren2016-09-27-4/+4
| | | | | | | | | | | | | This brings in a few minor fixes since the last sync. The largest change is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock doesn't actually exist. Remaining deltas: * Addition of u-boot,dm-pre-reloc property to a couple of nodes. * Addition of the NAND controller, which Linux doesn't yet support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: remove "0, " from DT unit addressesStephen Warren2016-09-27-82/+82
| | | | | | | | | Apparently the unit address in a DT node name is now supposed to be a single integer value, rather than a comma-separated list of individual cell values. Fix the U-Boot DTs to comply with this naming convention. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: Add DM_MMC support to Tegra MMC driverTom Warren2016-09-27-243/+70
| | | | | | | | | | | Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: set MMC pin mux in board_init()Stephen Warren2016-09-27-7/+5
| | | | | | | | | Most other pin mux is configured in this function. This removes the need to do it in an MMC-specific initialization function, which is good since that function is going away later in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: priv struct and naming cleanupStephen Warren2016-09-27-157/+161
| | | | | | | | | | | | | | | | | | | | struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: don't use periph_id in pad_init_mmc()Stephen Warren2016-09-27-4/+3
| | | | | | | | | | | The MMC driver will soon be converted to use standard clock/reset APIs, and so the periph_id field in the MMC device priv struct will disappear. Rework the implementation of pad_init_mmc() to rely on this; using the device register address is a much more direct test anyway. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: move pad_init_mmc() into MMC driverStephen Warren2016-09-27-36/+28
| | | | | | | | | | pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: use correct alias for SDHCI/MMC nodesStephen Warren2016-09-27-53/+53
| | | | | | | | | | | | | | | The Tegra MMC driver currently honors "sdhci" entries in /aliases. The MMC core however uses "mmc" entries in /aliases. This difference will be relevant once the Tegra MMC driver is converted to DM, and the MMC core handles alias lookups. To avoid issues during that conversion, fix the Tegra MMC driver and all Tegra DTs to use the same alias name as the MMC core does. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: fdt: Add 'non-removable' property to all eMMC nodesTom Warren2016-09-27-0/+13
| | | | | | | | | | | During debug of the DM_MMC changes to the Tegra MMC driver, I noticed that the 'removable' property wasn't being set correctly for the eMMC parts on most Tegra boards. Since the kernel DTS has this property set correctly, it should be in U-Boot's Tegra DT too. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: tegra: increase console buffer size and sys args numBryan Wu2016-09-27-2/+3
| | | | | | | | | | | | | | | | | | | | The Linux-for-Tegra kernel uses a very long command line. The default value of CONFIG_SYS_CBSIZE is too small to printf out the long command line and causes a message like: bootarg overflow 602+0+0+1 > 512 on the console, and the board refuses to boot. The default value of CONFIG_SYS_MAXARGS is too small to add a long long command line, and the kernel won't boot without the complete bootargs. Increasing these two config options solves this problem. Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Peter Chubb <Peter.Chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-885/+4733
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv7: ls102xa: Rename GIC_ADDR and DCSR_RCPM_ADDRYork Sun2016-09-26-4/+4
| | | | | | | | | | | | | | | | | | Instead of using CONFIG_* name space, rename these two macros to SYS_FSL_* space. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv7: ls1021a: Convert CONFIG_LS1_DEEP_SLEEP to Kconfig optionYork Sun2016-09-26-2/+5
| | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046ardb_emmc: Fix a typo in defconfigYork Sun2016-09-26-1/+1
| | | | | | | | | | | | | | | | It should be EMMC_BOOT instead of CONFIG_EMMC_BOOT. Signed-off-by: York Sun <york.sun@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun2016-09-26-2/+17
| | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
| * armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun2016-09-26-10/+17
| | | | | | | | | | | | | | | | | | Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-26-73/+87
| | | | | | | | | | | | | | | | | | Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun2016-09-26-6/+12
| | | | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-5/+1866
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu2016-09-14-0/+1470
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: disable SATA ECC in DCSRShaohui Xie2016-09-14-0/+4
| | | | | | | | | | | | | | | | | | This is a workaround to fix SATA CRC error. Once the root cause is found the ECC disabling will be removed. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable DDR erratum for ls1046aShengzhou Liu2016-09-14-0/+6
| | | | | | | | | | | | | | | | | | Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: spl: remove BSS clearing and board_init_rQianyu Gong2016-09-14-5/+0
| | | | | | | | | | | | | | | | | | | | As per the top level U-Boot README "Board Initialisation Flow" section, board_init_f() should return without calling board_init_r() directly. Clearing BSS and calling board_init_r() will be done in crt0_64.S. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie2016-09-14-0/+2
| | | | | | | | | | | | | | | | The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latencyMingkai Hu2016-09-14-0/+15
| | | | | | | | | | | | | | | | | | | | | | According to design specification, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, so increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * Export memset for standalone AQ FW load appsShaohui Xie2016-09-14-1/+2
| | | | | | | | | | | | | | | | | | | | The 'commit 95279315076c ("board/ls2085rdb: Export functions for standalone AQ FW load apps")' mentioned memset was exported but it was not, this patch exports the memset. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ddr: fsl: fix a compile issueShaohui Xie2016-09-14-1/+6
| | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that temp32 undeclared, this patch fixes it. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-409/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-1/+7
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-2/+284
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add EPU Finite State MachineHongbo Zhang2016-09-14-0/+165
| | | | | | | | | | | | | | | | The EPU Finite State Machie (FSM) is used in both the last stage of system suspend and the earliest stage of system resume. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add registers definition for system sleepHongbo Zhang2016-09-14-1/+60
| | | | | | | | | | | | | | | | This patch adds definitions of all the regesters necessary for system sleep. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: psci: make v7_flush_dcache_all public for all psci codeHongbo Zhang2016-09-14-3/+5
| | | | | | | | | | | | | | | | | | | | | | The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-323/+1
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+65
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+30
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set individual device access permissionHou Zhiqiang2016-09-14-14/+21
| | | | | | | | | | | | | | | | Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-36/+10
| | | | | | | | | | | | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-9/+276
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1043ardb: PPA: add PPA validation in case of secure bootSumit Garg2016-09-14-0/+39
| | | | | | | | | | | | | | | | | | | | As part of Secure Boot Chain of trust, PPA image must be validated before the image is started. The code for the same has been added. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: ls1043ardb: move sec_init to board_initSumit Garg2016-09-14-15/+17
| | | | | | | | | | | | | | | | | | | | sec_init() which was earlier called in misc_init_r() is now done in board_init() before PPA init as SEC block will be used during PPA image validation. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Revise workaround A008511 for A009803York Sun2016-09-14-36/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off. Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * driver/ddr/fsl: Add more debug registersYork Sun2016-09-14-6/+5
| | | | | | | | | | | | | | 32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * armv8: fsl-layerscape: Update ddr erratum a008336Shengzhou Liu2016-09-14-2/+4
| | | | | | | | | | | | | | | | | | DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * net: fm: fix spi flash probe for using driver modelQianyu Gong2016-09-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | The current code would always use the speed and mode set by CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using SPI driver model it should get the values from DT. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | kconfig: introduce kconfig for UBIHeiko Schocher2016-09-26-76/+251
| | | | | | | | | | | | | | | | | | move the UBI config options into Kconfig. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andrew F. Davis <afd@ti.com> Reviewed by: Evgeni Dobrev <evgeni at studio-punkt.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-coldfireTom Rini2016-09-26-2/+30
|\ \
| * | board: amcore: update to use dm serial driverAngelo Dureghello2016-09-25-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update amcore board to use dm serial driver. Signed-off-by: Angelo Dureghello <angelo@sysam.it> --- Changes for v2: - None
| * | board: amcore: add update scriptsAngelo Dureghello2016-09-25-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add some useful update scripts. Signed-off-by: Angelo Dureghello <angelo@sysam.it> --- Changes for v.2: - Fix syntax error on upgrade_jffs2 script
generated by cgit v1.1 at 2024-11-09 15:35:11 +0000