| Commit message (Collapse) | Author | Age | Lines |
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This patch adds support for calling a plattform dependant
pci_pre_init() function for 405 boards. This can be used to
move the current pci_405gp_fixup_irq() function into the
board code.
This patch also makes the CFG_PCI_PRE_INIT define obsolete.
A default function with 'weak' attribute is used when
a board specific pci_pre_init() is not implemented.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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The recently extended program_tlb() function had a problem when
multiple TLB's had to be setup (for example with 512MB of SDRAM). The
virtual address was not incremented. This patch fixes this issue
and is tested on Katmai with 512MB SDRAM.
Signed-off-by: Stefan Roese <sr@denx.de>
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- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
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Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Most prominently this changes 'erase' to be non-repeatable.
Signed-off-by: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Detlev Zundel <dzu@denx.de>
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This patch adds a board command to configure the I2C bootstrap EEPROM
values. Right now 533 and 667MHz are supported for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 533 nor ;to configure the board for 533MHz NOR booting
=> bootstrap 667 nand ;to configure the board for 667MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
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The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Now CONFIG_440 has to be defined in all PPC440 board config files.
Signed-off-by: Stefan Roese <sr@denx.de>
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- Introduced dedicated switches for building 440 and 405 images required
for 440-specific machine instructions like 'rfmci' etc.
- Exception vectors moved to the proper location (_start moved away from
the critical exception handler space, which it occupied)
- CriticalInput now serviced (with default handler)
- MachineCheck properly serviced (added a dedicated handler and return
subroutine)
- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
unhandled and those not relevant for 4xx were eliminated)
- Eliminated Linux leftovers, removed dead code
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds initial support for the Liebherr lwmon5 board euqipped
with an AMCC 440EPx PowerPC.
Signed-off-by: Stefan Roese <sr@denx.de>
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The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
is extended with the default GPIO output state (level).
Signed-off-by: Stefan Roese <sr@denx.de>
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Now program_tlb() allows to program a TLB (or multiple) with
different virtual and physical addresses. With this change, now one
physical region (e.g. SDRAM) can be mapped 2 times, once with caches
diabled and once with caches enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
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Set the correct value in GPIOx_TCR when configuring the gpio
with CFG_440_GPIO_TABLE.
Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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e600 does not have a bootpg restriction.
Move the version string to beginning of image at fff00000.
Resetvec.S is not needed.
Update flash copy instructions.
Add tftpflash env variable
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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The OBJTREE != SRCTREE build scenario was broken.
This fixes it.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
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The attached patch is mainly cosmetic, allowing u-boot to
display the correct bootstrap option letter according to the
datasheets.
The original patch was extended with 405EZ support by Stefan
Roese.
Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.
Signed-off-by: Stefan Roese <sr@denx.de>
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The U-Boot NAND booting support is now extended to support ECC
upon loading of the NAND U-Boot image.
Tested on AMCC Sequoia (440EPx) and Bamboo (440EP).
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch updates the "normal" Bamboo NOR booting port, so
that it is compatible with the coming soon NAND booting
Bamboo port.
It also enables the 2nd NAND flash on the Bamboo.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds hardware ECC support to the NDFC driver. It also
changes the register access from using the "simple" in32/out32
functions to the in_be32/out_be32 functions, which make sure
that the access is correctly synced. This is the only recommended
access to SoC registers in the current Linux kernel.
Signed-off-by: Stefan Roese <sr@denx.de>
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