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* mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro defineWills Wang2016-05-31-1/+2
| | | | | | Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip. Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: ath79: Add support for ungating USB and ethernet on qca953xWills Wang2016-05-31-0/+50
| | | | | | Add code to ungate USB and ethernet controller on qca953x Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: ath79: Use 8MB flash profile for mtd partition by defaultWills Wang2016-05-31-5/+5
| | | | | | Change bootm flash address and mtd partition table for 8MB flash profile. Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: ath79: ap121: Enable ethernetWills Wang2016-05-31-4/+16
| | | | | | | This patch enable network function for ap121 board. Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
* mips: ath79: Rename get_bootstrap into ath79_get_bootstrapWills Wang2016-05-31-28/+15
| | | | | | | | Add a platform prefix for function name in order to make more readable, and move it into ath79.h Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
* MIPS: malta: add defconfigs for MIPS64Daniel Schwierzeck2016-05-31-0/+33
| | | | | | | Add defconfigs for recently introduced MIPS64 support on Malta boards to get more build coverage for MIPS64. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Abstract cache op loops with a macroPaul Burton2016-05-31-41/+18
| | | | | | | | | | | The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Split I & D cache line size configPaul Burton2016-05-31-28/+53
| | | | | | | | | | | | Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Move cache sizes to KconfigPaul Burton2016-05-31-53/+95
| | | | | | | | | | | | Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: remove dead code from asm/u-boot-mips.hDaniel Schwierzeck2016-05-31-18/+3
| | | | | | | | Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* net: Add ag7xxx driver for Atheros MIPSMarek Vasut2016-05-31-0/+990
| | | | | | | | | | | | Add ethernet driver for the AR933x and AR934x Atheros MIPS machines. The driver could be easily extended to other WiSoCs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Wills Wang <wills.wang@live.com> [fixed Kconfig dependency] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: add tune for MIPS 34kcDaniel Schwierzeck2016-05-31-0/+4
| | | | | | Add tune Kconfig option for MIPS 34kc. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: provide a default u-boot-spl.ldsDaniel Schwierzeck2016-05-31-2/+93
| | | | | | | | | | | | Provide a default linker script for SPL binaries. Start address and size of text section and BSS section are configurable. All sections are arranged in a way that only relevant sections are kept in the code section for maximum size reduction. All other sections are kept but moved outside the code section to help with debugging. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* malta: Allow MIPS64 buildsPaul Burton2016-05-31-12/+25
| | | | | | | | Both real Malta boards & emulators that mimic Malta (eg. QEMU) can support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards, which enables the user to make use of the whole 64 bit address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* net: pcnet: Fix init on big endian 64 bitPaul Burton2016-05-31-3/+3
| | | | | | | | | | If dev->iobase is 64 bits wide then writing the value of the BAR into a pointer to iobase will not work on big endian systems, where the BAR value will incorrectly get written to the upper 32 bits of the 64 bit variable. Fix this by reading the BAR into a u32, matching the type expected by pci_read_config_dword. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* net: pcnet: Make 64 bit safePaul Burton2016-05-31-8/+10
| | | | | | | | Fix the pcnet driver to build safely on 64 bit platforms, in preparation for allowing MIPS64 builds for Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: pcnet: Stop converting kseg1->kseg0 addressesPaul Burton2016-05-31-9/+6
| | | | | | | | Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop manually converting addresses to their kseg0 equivalents in the pcnet driver. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Use CPHYSADDR to implement mips32 virt_to_physPaul Burton2016-05-31-4/+1
| | | | | | | | | | | | | | | | | | Use CPHYSADDR to implement the virt_to_phys function for converting from a virtual to a physical address for MIPS32, much as is already done for MIPS64. This allows for virt_to_phys to work regardless of whether the address being translated is in kseg0 or kseg1, unlike the previous subtraction based approach which only worked for addresses in kseg0. This allows for drivers to provide an address to virt_to_phys without needing to manually ensure that kseg1 addresses are converted to equivalent kseg0 addresses first. This patch is equivalent to this Linux patch currently waiting to be reviewed & merged: https://patchwork.linux-mips.org/patch/12564/ Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-05-27-510/+1272
|\ | | | | | | | | | | | | | | | | | | | | | | | | For odroid-c2 (arch-meson) for now disable designware eth as meson now needs to do some harder GPIO work. Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: lib/efi_loader/efi_disk.c Modified: configs/odroid-c2_defconfig
| * dm: rockchip: Enable CONFIG_BLKSimon Glass2016-05-27-0/+3
| | | | | | | | | | | | | | Enable CONFIG_BLK to move to using driver model for block devices. This affects MMC booting in SPL, as well as MMC access in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: mmc: Use cfg directly in mmc_bind()Simon Glass2016-05-27-1/+1
| | | | | | | | | | | | This small change tidies up the code slightly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: mmc: Fix up mmc_bread/bwrite() prototypes for SPLSimon Glass2016-05-27-0/+14
| | | | | | | | | | | | | | When these functions are not compiled in, we still need to declare the correct function signature to avoid a build warnings in SPL. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: rockchip: mmc: Allow use of CONFIG_BLKSimon Glass2016-05-27-0/+31
| | | | | | | | | | | | Allow driver model to be used for block devices in the rockchip mmc driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: mmc: dwmmc: Support CONFIG_BLKSimon Glass2016-05-27-15/+34
| | | | | | | | | | | | Add support for using driver model for block devices in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: mmc: spl: Add support for CONFIG_BLKSimon Glass2016-05-27-5/+4
| | | | | | | | | | | | Allow driver model to be used for block devices in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: efi: Update for CONFIG_BLKSimon Glass2016-05-27-16/+47
| | | | | | | | | | | | | | | | This code does not currently build with driver model enabled for block devices. Update it to correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexander Graf <agraf@suse.de>
| * dm: mmc: Convert sdhci to support CONFIG_BLKSimon Glass2016-05-27-1/+1
| | | | | | | | | | | | Update sdhci.c so that it works with driver model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: env: mmc: Convert env_mmc to support CONFIG_BLKSimon Glass2016-05-27-4/+4
| | | | | | | | | | | | | | Update the MMC environment code so that it works with driver-model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Drop SPL GPIO support for rk3288Simon Glass2016-05-27-1/+0
| | | | | | | | | | | | This is not currently used and saves a little over 1KB of SPL image size. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: video: Flush the cache when the display is updatedSimon Glass2016-05-27-0/+1
| | | | | | | | | | | | | | Enable this option to correct display artifacts when a write-back cache is in use. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Drop unnecessary SPL propertiesSimon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | While we consider whether to drop use of DT in SPL, remove some unwanted properties. This reduces SPL size by about 250 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Check image name for the rksd imageSimon Glass2016-05-27-6/+1
| | | | | | | | | | | | | | We need a correct name (rk3288, rk3036) so check this to avoid a crash later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * mmc: Use byte array for multipliersSimon Glass2016-05-26-1/+1
| | | | | | | | | | | | | | We don't need an int since no value is over 80. This saves a small amount of SPL space (about 44 bytes). Signed-off-by: Simon Glass <sjg@chromium.org>
| * mmc: Drop dead mmc code for non-generic MMCSimon Glass2016-05-26-66/+0
| | | | | | | | | | | | | | All boards that use MMC define CONFIG_GENERIC_MMC now, so we can drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * mmc: Drop mmc_register()Simon Glass2016-05-26-10/+0
| | | | | | | | | | | | This function is no longer used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * reset: Drop the reset failure messageSimon Glass2016-05-26-1/+1
| | | | | | | | | | | | This adds to code size and is not needed, since hang() will print a message. Signed-off-by: Simon Glass <sjg@chromium.org>
| * tiny-printf: Support snprintf()Simon Glass2016-05-26-2/+25
| | | | | | | | | | | | | | | | Add a simple version of this function for SPL. It does not check the buffer size as this would add to the code size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * tiny-printf: Tidy up a few nitsSimon Glass2016-05-26-8/+8
| | | | | | | | | | | | | | | | | | - Rename 'w' to 'width' to make it more obvious what it is used for - Use bool and int types instead of char to avoid register-masking on 32-bit machines Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size infoSimon Glass2016-05-26-0/+1
| | | | | | | | | | | | | | | | This shows a proper progress display and the total amount of data transferred. Enable it for Raspberry Pi. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
| * mailbox: implement a sandbox testStephen Warren2016-05-26-0/+234
| | | | | | | | | | | | | | | | | | This adds a sandbox mailbox implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> # v1
| * Add a mailbox driver framework/uclassStephen Warren2016-05-26-0/+431
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A mailbox is a hardware mechanism for transferring small message and/or notifications between the CPU on which U-Boot runs and some other device such as an auxilliary CPU running firmware or a hardware module. This patch defines a standard API that connects mailbox clients to mailbox providers (drivers). Initially, DT is the only supported method for connecting the two. The DT binding specification (mailbox.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Rename reset to sysresetStephen Warren2016-05-26-315/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * sunxi: gpio: convert bind() to use driver dataStephen Warren2016-05-26-40/+50
| | | | | | | | | | | | | | | | | | | | | | Now that the DM core sets driver_data before calling bind(), this driver can make use of driver_data to determine the set of child devices to create, rather than manually re-implementing the matching logic in code. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
| * dm: allow setting driver_data before/during bindStephen Warren2016-05-26-14/+62
| | | | | | | | | | | | | | | | | | | | | | This will allow a driver's bind function to use the driver data. One example is the Tegra186 GPIO driver, which instantiates child devices for each of its GPIO ports, yet supports two different HW instances each with a different set of ports, and identified by the udevice_id .data field. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-05-27-8/+182
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| * | rockchip: rock2: dts: use status = "okay" not okSjoerd Simons2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | u-boot only recognize okay to enable a node (Linux seems to be more lenient here). So use okay instead. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288-firefly: Add gmac definitionSjoerd Simons2016-05-27-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Add a definition for the gmac interface to the firefly device-tree. Copied verbatim from the linux kernel. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3Sjoerd Simons2016-05-27-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various GMAC related fields. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock support for the gmac ethernet interfaceSjoerd Simons2016-05-27-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: pinctrl: support more pinsSjoerd Simons2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size of the cell array to accomedate that, otherwise only the first 10 get configured. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-14 21:51:07 +0000