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* dm: usb: Use blk_dread/write() instead of direct callsSimon Glass2016-07-27-2/+2
| | | | | | Update the USB mass storage code to allow it to work with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: socfpga: mmc: Support CONFIG_BLKSimon Glass2016-07-27-1/+31
| | | | | | Update the driver to support using driver model for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: zynq: Convert zynq to use driver model for MMCSimon Glass2016-07-27-5/+39
| | | | | | | Move zynq to the latest driver model support by enabling CONFIG_DM_MMC, CONFIG_DM_MMC_OPS and CONFIG_BLK. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: zynq: usb: Convert to CONFIG_DM_USBSimon Glass2016-07-27-52/+53
| | | | | | Convert zynq USB to driver model. Note this is tested on zynq-zybo only. Signed-off-by: Simon Glass <sjg@chromium.org>
* zynq: Increase the early malloc() sizeSimon Glass2016-07-27-0/+7
| | | | | | This is needed to support driver-model conversion of USB and block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: phy: marvell: Add a missing errno.h headerSimon Glass2016-07-27-0/+1
| | | | | | This corrects a build error on zynqmp. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Show early-malloc() usage in bdinfoSimon Glass2016-07-27-0/+5
| | | | | | | | | | | | | This is useful information to show how close we are to the limit. At present it is only available by enabling DEBUG in board_r.c. Make it available with the 'bdinfo' command also. Note that this affects ARM only. The bdinfo command is different for each architecture. Rather than duplicating the code it would be better to refactor it (as was done with global_data). Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass2016-07-27-131/+25
| | | | | | | Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass2016-07-27-51/+20
| | | | | | | This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add a function to bind child devicesSimon Glass2016-07-27-0/+25
| | | | | | | | | | | | | | We currently use dm_scan_fdt_node() to bind devices. It is an internal function and it requires the caller to know whether we are pre- or post- relocation. This requirement has become quite common in drivers, so the current function is not ideal. Add a new function with fewer arguments, that does not require internal headers. This can be used directly as a post_bind() method if needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: dwmmc: use the callback functions as staticJaehoon Chung2016-07-27-5/+2
| | | | | | | | | There are no places to call these functions. It should be used the callback function. Then it can be used as static functions. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: mmc: dwmmc: fix the wrong explanation for clock valuesJaehoon Chung2016-07-27-4/+4
| | | | | | | This e,g is wrong. Maximum/minimum e.g values are swapped each other. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-26-15/+111
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| * sunxi: Disable sun8i emac driverHans de Goede2016-07-27-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable the sun8i emac driver for now, there are 2 issues with it: 1) It is causing issues with network connectivity under the kernel driver, when booting the kernel with v2 of Corentin's sun8i-h3 emac driver, I get the connection status bouncing between connected at 100mbps full-duplex and being down every second. The second issue is that when trying to use it from u-boot I get a number of unaligned cache flush errors: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * net: sun8i_emac: Drop redundant and incorrect setting of syscon registerChen-Yu Tsai2016-07-26-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * net: sun8i_emac: Do not configure AHB2 clockChen-Yu Tsai2016-07-26-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add EMAC ethernet0 alias for H3 dtsiChen-Yu Tsai2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | The sunxi ethernet address generation code looks for ethernet[0-3] aliases to find ethernet controllers to generate MAC addresses for. Without a valid address, the driver fails to register. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add defconfig and dts file for the Orange Pi PC Plus SBCHans de Goede2016-07-26-1/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a new Orange Pi PC *Plus* version available now, this is an extended version of the regular Orange Pi PC with sdio wifi and an eMMC. The upstream kernel devs have decided that they want a separate dts for the PC Plus rather then sharing a single dts between the regular PC and the PC Plus. So add a new orangepi_pc_plus_defconfig to match. The added dts file matches the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: uniphier: move CONFIG_I2C_EEPROM to defconfigMasahiro Yamada2016-07-26-1/+12
| | | | | | | | | | | | | | We already have the entry for this option in Kconfig, so let's migrate to it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-mpc86xxTom Rini2016-07-26-1/+1
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| * | powerpc/86xx: Pass -mcpu=7400 to GCCScott Wood2016-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Without this, GCC uses the toolchain default, which may be incompatible with -maltivec. Signed-off-by: Scott Wood <oss@buserror.net> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-104/+887
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| * | | armv8: ls1043aqds: add IFC fixup in case QSPI is enabledQianyu Gong2016-07-26-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is enabled, IFC would not be initialized correctly. So disable the IFC node for Linux. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8/ls1043a: Add MTD partition schemeWenbin Song2016-07-26-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add and share the the MTD partition scheme with kernel by default bootargs. And add the "mtdparts" env. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv8/ls1046a: Cleanup the environment variablesWenbin Song2016-07-26-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup the variables: "kernel_addr","ramdisk_addr", "ramdisk_size","console". Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: mmu: Fix enabling MMUYork Sun2016-07-26-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: move secure text section into OCRAMHongbo Zhang2016-07-26-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-2/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: check target CPU ID before further operationsHongbo Zhang2016-07-26-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The input parameter CPU ID needs to be validated before furher oprations such as CPU_ON, this patch introduces the function to do this. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: add PSCI v1.0 functions skeletonHongbo Zhang2016-07-26-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | drivers: net/fm: Add Fman support for LS1046AMingkai Hu2016-07-26-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Fman module on LS1046A is similiar with that on LS1043A but LS1046A has one more XFI (10GbE) interface. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu2016-07-26-3/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl_lsch2: Add SerDes 2 supportQianyu Gong2016-07-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Consolidate the LSCH2 common definesQianyu Gong2016-07-26-39/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common configurations. So put the common define under FSL_LSCH2 to increase readability. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Add A72 core detectionAlison Wang2016-07-26-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1043aqds: Update MAINTAINERSYork Sun2016-07-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add ls1043aqds_lpuart_defconfig to file list. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls2080aqds: Update MAINTAINERSYork Sun2016-07-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add ls2080aqds_qspi_defconfig to file list. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | arm: ls1021atwr: Add SD secure boot targetSumit Garg2016-07-26-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SD secure boot target for ls1021atwr. Implement board specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-23/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-26-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | DM: crypto/fsl: Enable rsa DM driver usage before relocationSumit Garg2016-07-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable rsa signature verification in SPL framework before relocation for verification of main u-boot. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | include: usb: Rename USB controller base address mappingRajesh Bhagat2016-07-26-22/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | i2c: fsl: Fix driver initializationmario.six@gdsys.cc2016-07-26-5/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a oversight in testing, the initialization of the recently introduced Freescale I2C DM driver works only for 36 bit mode of e.g. the MPC85XX SoCs (specifically, if the physical addresses are 64 bit wide and the DT addresses 32 bit wide). This patch corrects the initialization so that it will work in a more general setting. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-07-26-360/+898
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| * | | i2c: mvtwsi: Add documentationmario.six@gdsys.cc2016-07-26-19/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add full documentation to all driver functions. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | i2c: mvtwsi: Make delay times frequency-dependentmario.six@gdsys.cc2016-07-26-42/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices using the MVTWSI driver have the option to run at speeds faster than Standard Mode (100kHZ). On the Armada 38x controllers, this is actually necessary, since due to erratum FE-8471889, a timing violation concerning repeated starts prevents the controller from working correctly in Standard Mode. One of the workarounds recommended in the erratum is to set the bus to Fast Mode (400kHZ) operation and ensure all connected devices are set to Fast Mode. In the current version of the driver, however, the delay times are hard-coded to 10ms, corresponding to Standard Mode operation. To take full advantage of the faster modes, we would need to either keep the currently configured I2C speed in a globally accessible variable, or pass it to the necessary functions as a parameter. For DM, the first option is not a problem, and we can simply keep the speed in the private data of the driver. For the legacy interface, however, we would need to introduce a static variable, which would cause problems with boots from NOR flashes; see commit d6b7757 "i2c: mvtwsi: Eliminate twsi_control_flags." As to not clutter the interface with yet another parameter, we therefore keep the default 10ms delays for the legacy functions. In DM mode, we make the delay time dependant on the frequency to allow taking full advantage of faster modes of operation (tested with up to 1MHZ frequency on Armada MV88F6820). Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | i2c: mvtwsi: Handle zero-length offsets properlymario.six@gdsys.cc2016-07-26-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zero-length offsets are not properly handled by the driver. When a read operation with a zero-length offset is started, a START condition is asserted, and since no offset bytes are transferred, a repeated START is issued immediately after, which confuses the controller. To fix this, we send the first START only if any address bytes need to be sent, and keep track of the expected start status accordingly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | i2c: mvtwsi: Add compatibility to DMmario.six@gdsys.cc2016-07-26-1/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary functions and Kconfig entry to make the MVTWSI I2C driver compatible with the driver model. A possible device tree entry might look like this: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; clock-frequency = <100000>; u-boot,i2c-slave-addr = <0x0>; }; Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | i2c: mvtwsi: Make address length variablemario.six@gdsys.cc2016-07-26-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The length of the address parameter of the __twsi_i2c_read and __twsi_i2c_write functions is fixed to four bytes. As a final step in the preparation of the DM conversion, we make the length of this parameter variable by turning it into an array of bytes, and convert the 32 bit value that's passed to the legacy functions into a four-byte-array on the fly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | i2c: mvtwsi: Factor out adap parametermario.six@gdsys.cc2016-07-26-51/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be able to use the compatibility layer from the DM functions, we factor the adap parameter out of all functions, and pass the actual register base instead. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-02 06:03:27 +0000