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* udoo_neo: Remove USDHC3 supportBreno Lima2016-12-16-89/+6
| | | | | | | | It's not necessary to support USDHC3 in U-Boot as it's being used for the WLAN. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* arm: imx: initial support for colibri imx6Max Krummenacher2016-12-16-0/+2449
| | | | | | | | This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* arm: imx: initial support for apalis imx6Max Krummenacher2016-12-16-0/+2691
| | | | | | | | This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* ARM: dts: vf: Fix warning about missing reg propertyStefan Agner2016-12-16-0/+2
| | | | | | | | | Add proper reg values for the two AIPS bus nodes. This avoids this two warnings: Node /soc/aips-bus@40000000 has a unit name, but no reg property Node /soc/aips-bus@40080000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* colibri_vf: use same NAND clock as Linux usesStefan Agner2016-12-16-1/+1
| | | | | | | | | | | | | | | | Currently a divider of 6 has been used, leading to following NAND Flash Controller (NFC) clocks: VF61: 27.7 MHz (166.7MHz bus clock) VF50: 22 MHz (132MHz bus clock) The NAND Flash Memory used on VF50 allows to use clock speed of up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can use the same divider of 4 on both modules to configure the maximal possible clock speeds: VF61: 41.7 MHz VF50: 33 MHz Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* colibri_vf: cleanup USB clock initializationStefan Agner2016-12-16-4/+10
| | | | | | | | | Use the same preprocessor define to enable clocks as we use to enable the driver. Make sure that the necessary PLL's are on (they get enabled by boot ROM by default, so this is more for completness). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* colibri_vf: use device-tree for MTD partitionsStefan Agner2016-12-16-0/+13
| | | | | | | | Use device-tree fixup to communicate the MTD partitions to the kernel. U-Boot's mtdparts environment variable will be used as partition source for the device-tree based partition table too. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* toradex: allow custom fdt board setup in board fileStefan Agner2016-12-16-5/+53
| | | | | | | | | | The config block support currently uses the ft_board_setup function to patch the device tree with config block information. However, this does not allow to patch the device tree with board specific information. Rename the common setup function to ft_common_board_setup and use the call it from the board files directly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* toradex: fix USB Download gadget fixup callbackStefan Agner2016-12-16-2/+2
| | | | | | | Use the proper config option to guard the USB Download Function fixup callback. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-12-16-3765/+9059
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| * MAINTAINERS: DFU: Change e-mail address for DFU maintainerLukasz Majewski2016-12-12-1/+1
| | | | | | | | | | | | | | Despite I leave Samsung by the end of the year, I'm going to maintain DFU in u-boot. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * MAINTAINERS: ONENAND: MTD: Mark Samsung's OneNAND as orphanedLukasz Majewski2016-12-12-2/+2
| | | | | | | | | | | | | | | | | | Since I leave Samsung by the end of the year, I will not have access to OneNAND devices anymore. Hence the custodian position has been marked as "Orphaned". Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-64/+1800
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| | * arm64: mvebu: Enable hush parser in A8K default configurationKonstantin Porotchkin2016-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hush parser in Armada-7040 and Armada-8040 DB default configurations. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Enable PCIe support in Armada-7040 configurationKonstantin Porotchkin2016-12-12-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCIe bus support in Armada-7040 DB default configuration Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Add L3 cache flush functionality to A8K familyKonstantin Porotchkin2016-12-12-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Enable pin control support in A8K default configKonstantin Porotchkin2016-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mvebu pin control support in the default configuration files for Armada-7040 and Armada-8040 development boards Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Enable BUBT command support in A8K default configKonstantin Porotchkin2016-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mvebu "bubt" command support in the default configuration file for Armada-7040 and Armada-8040 development boards Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Add pin control nodes to A8K family DTS filesKonstantin Porotchkin2016-12-12-22/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+651
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Add bubt command for flash image burnKonstantin Porotchkin2016-12-12-0/+896
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for mvebu bubt command for flash image load, check and burn on boot device. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Modify the A8K SPI and I2C config in DTSKonstantin Porotchkin2016-12-12-67/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the Armada-8040-db and Armada-7040-db SPI and I2C DTS settings with latest DB settings: - 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO) - 8040-db: disable cps_i2c0 on CP1 - 8040-db: enable spi1 on CP1 (the new location of the boot flash) The spi1 on CP1 is aliased as spi0 since this is the way the driver enumerates it. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-12-12-1857/+2697
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| | * | ARM: uniphier: remove BLK selectMasahiro Yamada2016-12-11-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a user configurable option, but "select BLK" forces users to enable it. Even with this commit, BLK is still enabled by "default y if DM_MMC" for UniPhier SoCs; the difference is users can disable it if they do not need it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: dts: uniphier: sync Device Tree with LinuxMasahiro Yamada2016-12-11-1851/+2684
| | | | | | | | | | | | | | | | | | | | | | | | Sync with the latest kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: disable CONFIG_ARCH_FIXUP_FDT_MEMORYMasahiro Yamada2016-12-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not overwrite the memory nodes in the kernel DT where some parts of the memory region might be carved out. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: remove unneeded parenthesesMasahiro Yamada2016-12-10-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Just a cosmetic cleanup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: remove unneeded initializerMasahiro Yamada2016-12-10-2/+4
| | |/ | | | | | | | | | | | | | | | This will be used to store the return value of readl(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | imgtec: Update MAINTAINERS for more config filesTom Rini2016-12-09-1/+6
| | | | | | | | | | | | | | | | | | Cover all of the boston and malta variations. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evmJyri Sarha2016-12-09-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | calimain: Update maintainers and their email addressesChristian Riesch2016-12-09-2/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Christian Riesch <christian@riesch.at> Cc: Manfred Rudigier <manfred.rudigier@omicronenergy.com> Cc: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
| * | travis-ci: Switch to building QEMUTom Rini2016-12-09-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are a number of features in newer QEMU that will allow us to test a wider range of platforms, so we want to use at least v2.8.0. Second, making use of a PPA for QEMU fails from time to time. So we change to checking out and building a copy of QEMU when we know that we are going to use test.py and need QEMU to be installed. This adds around 4 minutes per test.py job that we run. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | tools: mkimage: Use fstat instead of stat to avoid malicious hacksMichal Simek2016-12-09-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch is fixing: "tools: mkimage: Check if file is regular file" (sha1: 56c7e8015509312240b1ee15f2ff74510939a45d) which contains two issues reported by Coverity Unchecked return value from stat and incorrect calling sequence where attack can happen between calling stat and fopen. Using pair in opposite order (fopen and fstat) is fixing this issue because fstat is using the same file descriptor (FILE *). Also fixing issue with: "tools: mkimage: Add support for initialization table for Zynq and ZynqMP" (sha1: 3b6460809c2a28360029c1c48247648fac4455c9) where file wasn't checked that it is regular file. Reported-by: Coverity (CID: 154711, 154712) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | davinci: omapl138_lcdk: boot from zImageFabien Parent2016-12-09-4/+6
| | | | | | | | | | | | | | | | | | | | | Stop booting legacy uImage and now boot zImage. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | defconfigs: am57xx_hs_evm: Add default OPTEE load addressAndrew F. Davis2016-12-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we let U-Boot find a spot at the end of DRAM at runtime, this forces us to build an OPTEE image based on the size of DRAM for an EVM. Add a default address that works across all current AM57xx EVMs. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | defconfigs: dra7xx_hs_evm: Add default OPTEE load addressAndrew F. Davis2016-12-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we let U-Boot find a spot at the end of DRAM at runtime, this forces us to build an OPTEE image based on the size of DRAM for an EVM. Add a default address that works across all current DRA7xx EVMs. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | davinci: omapl138_lcdk: fix bad NAND ECC configFabien Parent2016-12-09-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The configuration used to error correction was not in line with what linux and the ROM code is using. Fix it by using the correct configuration. Now u-boot and the SPL are able to read correctly anything written by them. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | davinci: omapl138_lcdk: increase u-boot load sizeFabien Parent2016-12-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | A size of 0x200 seems way too short for u-boot. Increase the size to 512k. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | cmd: pci: add option to parse and display BAR informationYehuda Yitschak2016-12-09-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PCI command only allows to see the BAR register values but not the size and actual base address. This little extension parses the BAR registers and displays the base, size and type of each BAR. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | spl: sandbox: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-14/+3
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: uniphier: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-5/+0
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: sunxi: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-9/+0
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Drop announce_boot_device()Simon Glass2016-12-09-83/+3
| | | | | | | | | | | | | | | | | | This task can be handled by inline code now. Drop this function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Pass the loader into spl_load_image()Simon Glass2016-12-09-4/+4
| | | | | | | | | | | | | | | | | | | | | Rather than have this function figure out the correct loader again, pass it in as a parameter. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Move the loading code into its own functionSimon Glass2016-12-09-12/+29
| | | | | | | | | | | | | | | | | | | | | Create a boot_from_devices() function to handle trying each device. This helps to reduce the size of the already-large board_init_r() function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-21/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Use a single underscore in the SPL_LOAD_IMAGE_METHOD() macroSimon Glass2016-12-09-7/+7
| | | | | | | | | | | | | | | | | | | | | A double underscore is normally reserved for compiler predefines. Use a single underscore instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | am57xx: Set tps659038 PMIC GPIO7 pad mux value to POWERHOLDKeerthy2016-12-09-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO7 pad mux should be programmed to POWERHOLD value as per board design. In cases where the PMIC is shut off the mux is set to GPIO7 mode. So during initialization to be on the safer side set the mode to POWERHOLD. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | configs: omap5_uevm_defconfig: Enable LPAE modeKeerthy2016-12-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: armv7: add us timer for bootstagePatrick Delaunay2016-12-09-1/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | solve issue when bootstage is used with armV7 generic timer first call of timer_get_boot_us() use the function get_timer() before timer initialization (arch.timer_rate_hz = 0) => div by 0 Commit-notes When I activate bootstage on ARMV7 architecture with platform using the generic armv7 timer defined in file ./arch/arm/cpu/armv7m/timer.c I have a issue because gd->arch.timer_rate_hz = 0 For me the get_timer() function should not used before timer_init (which initialize gd->arch.timer_rate_hz) at least for the ARMV7 timer. But in the init sequence, the first bootstage fucntion is called before timer_init and this function use the timer function. For me it is a error in the generic init sequence : mark_bootstage is called before timer_init. static init_fnc_t init_sequence_f[] = { .... arch_cpu_init_dm, mark_bootstage, /* need timer, go after init dm */ ... #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ defined(CONFIG_SPARC) timer_init, /* initialize timer */ #endif ....... To solve the issue for all the paltform, we can move timer_init() call just before mark_bootstage() in this array... It should be ok for ARMV7 but I don't sure for other platform impacted - the other ARM platform or ARMV7 wich don't use generic timer - MIPS BLACKFIN NDS32 or SPARC and I don't sure of impact for other function called (board_early_init_f for example....) => This patch solve issue only in timer armv7 get_boot_us() can be called everytime without div by 0 issue (gd->arch.timer_rate_hz is not used) END Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
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