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| | * mx6dlsabresd: Use its own DCD tableFabio Estevam2014-09-09-1/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently mx6dlsabresd shares the same DCD settings with the nitrogen board. Provide a DCD configuration file specific to mx6dlsabresd with the settings recommended by the Freescale hardware team. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * arm: vf610: lpuart: disable FIFO on initializatonStefan Agner2014-09-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
| | * arm: vf610: lpuart: fix status register handlingStefan Agner2014-09-09-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
| | * mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov2014-09-09-4/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| | * imximage: Fix imximage IVT bug for EIM-NOR bootYe.Li2014-09-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The load region size of EIM-NOR are defined to 0. For this case, the parameter "imximage_init_loadsize" must be calculated. The imximage tool implements the calculation in the "imximage_generate" function, but the following function "imximage_set_header" resets the value and not calculate. This bug cause some fields of IVT head are not correct, for example the boot_data and DCD overlay the application area. Signed-off-by: Ye.Li <B37916@freescale.com>
| | * iMX6: Disable the L2 before chaning the PL310 latencyYe.Li2014-09-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
| | * imx: ventana: Avoid undefined behaviourThierry Reding2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The leds array within struct ventana has space for 3 elements, but the setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent versions of GCC complain about that: board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio': board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations] if (gpio_cfg[board].leds[i]) ^ board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop for (i = 0; i < 4; i++) { ^ Fix this by making the upper bound of the loop match the array size. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
| | * tools: imximage: Fix the maximum DCD size for mx53/mx6Fabio Estevam2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to mx53 and mx6 reference manuals: "The maximum size of the DCD limited to 1768 bytes." As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and excluding the first entry, which is the header leads to 220 as the maximum number for DCD size. Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com>
| | * imx: ventana: add pci fixup for PLX PEX860x switch GPIOTim Harvey2014-09-09-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion. These boards use GPIO on the PLX device as PERST# for the downstream ports thus we assert this when the PLX is enumerated. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * pci: add support for board_pci_fixup_dev functionTim Harvey2014-09-09-0/+11
| | | | | | | | | | | | | | | | | | | | | Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * arm: mx6: cm_fx6: add sata supportNikita Kiryanov2014-09-09-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SATA. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: cm_fx6: use eepromNikita Kiryanov2014-09-09-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use Compulab eeprom module to obtain revision number, serial number, and mac address from the EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: cm_fx6: add i2c supportNikita Kiryanov2014-09-09-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for all 3 I2C busses on Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: cm_fx6: add usb supportNikita Kiryanov2014-09-09-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB and USB OTG host support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: cm_fx6: add ethernet supportNikita Kiryanov2014-09-09-2/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ethernet support for Compulab CM-FX6 CoM Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: cm_fx6: add nand supportNikita Kiryanov2014-09-09-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: add support for Compulab cm-fx6 CoMNikita Kiryanov2014-09-09-0/+819
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: add get_cpu_type()Nikita Kiryanov2014-09-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov2014-09-09-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov2014-09-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
| | * arm: mx6: ddr: do not write into reserved bitNikita Kiryanov2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: cleanupNikita Kiryanov2014-09-09-141/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov2014-09-09-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * sata: dwc_ahsata: implement sata_port_statusNikita Kiryanov2014-09-09-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata. Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * compulab: eeprom: add support for defining eeprom i2c busNikita Kiryanov2014-09-09-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * mx6: add clock enabling functionsNikita Kiryanov2014-09-09-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * imx: ventana: added cputype env varTim Harvey2014-09-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | There are many similarities between the IMX6QUAD/IMX6DUAL and there are many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env variable that tells you which type you have. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * imx: ventana: add GW5520 supportTim Harvey2014-09-09-7/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as: * 2x MiniPCIe sockets * 2x USB host sockets * 2x i210 GigE * HDMI out * digital I/O expansion Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * imx: ventana: base SPL MMDC calibration on width and size not boardTim Harvey2014-09-09-80/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 MMDC calibration registers depend on propagation delay and capacitive loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the board layout varies little in trace-lengths such that propagation delays are irrelevant thus we can simply things by using calibration values obtained from various board layouts based on a common SoC and DDR chip configuration. This eliminates board-model from being needed allowing more flexibility. These values were tested on a large sample size of Gateworks Ventana boards ranging in layout, and memory configuration over the entire temperature range supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * imx: ventana: updated notes regarding NAND boot errataTim Harvey2014-09-09-2/+3
| | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-09-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-09-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* | | Revert "ARM: SPL: do not set gd again"Tom Rini2014-09-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the high level, the problem is that we set gd multiple times (and still do, even after the commit we're reverting). We set important parts of gd to the copy which is not above stack but rather in the data section. For the release, we're going to revert this change and for the next release we shall correct things to only, really, set gd once to an appropriate location and ensure that comments about it are correct too. This reverts commit f0c3a6c4ad09210d5d4aeafe87685ee75e5683d6. Acked-by: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
* | | kconfig: armv8: move CONFIG_ARM64 to KconfigMasahiro Yamada2014-09-16-14/+18
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | vexpress64: kconfig: consolidate CONFIG_TARGET_VEXPRESS_AEMV8A_SEMIMasahiro Yamada2014-09-16-20/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Steve Rae <srae@broadcom.com> Cc: David Feng <fenghua@phytium.com.cn>
* | | net: dns: fix for DNS queries sent to the wrong MAC addressGerhard Sittig2014-09-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a DNS query is sent out, the ethernet packet can get directed to the MAC address of a server that was communicated to before. This is wrong when the previously stored MAC address corresponds to a different server's IP address, i.e. when the IP address of the previous and the current communication are different. The error can get reproduced by running a sequence of e.g. a TFTP download and a DNS query, where the TFTP and DNS servers reside on individual machines. The fix is to clear the server's MAC address that might be left from a previous operation, and to fetch the peer's MAC address in a new ARP lookup, before the DNS query is sent. This is the approach taken in other network services, like 8e52533d1095 ("net: tftpsrv: Get correct client MAC address"). Reported-by: Dirk Zimoch <dirk.zimoch@psi.ch> Signed-off-by: Gerhard Sittig <gsi@denx.de>
* | | kconfig: add sanity checks for SPL configurationMasahiro Yamada2014-09-16-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the SPL configuration, "make <dir>/<target>" is used. Here, <dir> is either "spl" or "tpl" <target> is one of "config", "menuconfig", "xconfig", etc. This commit adds two checks: [1] If <dir> is given an unsupported subimage, the configuration should error out like this: $ make qpl/menuconfig *** *** "make qpl/menuconfig" is not supported. *** [2] Make sure that "CONFIG_SPL" is enabled in the ".config" before running "make spl/menuconfig. Otherwise, the SPL image is not built at all. Having "spl/.config" makes no sense. In such a case, the configuration should exit with a message: $ make spl/menuconfig *** *** Create ".config" with "CONFIG_SPL" enabled *** before "make spl/menuconfig". *** Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Simon Glass <sjg@chromium.org>
* | | net: usb: Add SMSC copyright to smsc95xx driverSimon Glass2014-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver was upstreamed without an SMSC copyright, even thought it seems that SMSC was the original author. See the kernel version for a code comparison: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190 It's not clear who actually moved this code, or whether the kernel was the original source, or somewhere else, but it probably should still have the SMSC copyright. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREADmaxin.john@enea.com2014-09-16-2/+2
| | | | | | | | | | | | | | | | | | This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD Signed-off-by: Maxin B. John <maxin.john@enea.com>
* | | mtd: nand: davinci_nand: update write_page function for keystone RBLKhoronzhuk, Ivan2014-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After mtd was synced with Linux 3.14 (ff94bc40af3481d47546595ba73c136de6af6929) the number of parameters for write_page function of nand_chip was changed. The additional two var were needed for subpage write. As keystone has no supbage write they are not needed. So correct only function definition by upgrading it's parameter list. That helps to get ritd of compilation warning. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | | generic_board: do not set gd->fdt_blob unless CONFIG_OF_CONTROL=yMasahiro Yamada2014-09-16-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | gd->fdt_blob is used for FDT control of U-Boot. If CONFIG_OF_CONTROL is not defined, it is useless. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | kbuild: standalone: simplify clean-filesMasahiro Yamada2014-09-16-1/+1
| | | | | | | | | | | | | | | | | | | | | Files added $(extra-) are removed by "make clean". Besides, wildcard "*.srec *.bin" is simpler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | scripts/Makefile.clean: clean also $(extra-m) and $(extra-)Masahiro Yamada2014-09-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This commit is a backport from Linux Kernel, commit 9d5db8949f1ecf4019785b04d8986835d3c0e99e, written by me. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | kconfig: show an error message when defconfig is not foundMasahiro Yamada2014-09-16-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a non-existing defconfig is specified, display an easy-to-understand message (fake the error message on Linux Kernel): $ make foo_defconfig *** *** Can't find default configuration "confis/foo_defconfig"! *** Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | | common: fix include guards for CONFIG_MPGabriel Huau2014-09-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was breaking the build for some boards: MPC8536DS MPC8536DS_36BIT MPC8536DS_SDCARD MPC8536DS_SPIFLASH qemu-ppce500 Include only these features for some PPC boards if the configuration for MultiProcessor is enabled. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Cc: Tom Rini <trini@ti.com> Cc: York Sun <yorksun@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | kconfig: fix a bug of "make config"Masahiro Yamada2014-09-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 3ff291f371fa9858426774f3732924bacb61ed1c (kconfig: convert Kconfig helper script into a shell script), "make config" is not working because of a missing '$' before '(Q)'. Besides, "make config" should be invoked via scripts/multiconfig.sh to avoid a warning message: Kconfig:11:warning: environment variable KCONFIG_OBJDIR undefined Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | kconfig: fix savedefconfig to handle TPL correctlyMasahiro Yamada2014-09-16-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 3ff291f371fa9858426774f3732924bacb61ed1c (kconfig: convert Kconfig helper script into a shell script), "make savedefconfig" of TPL boards has not been working. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.o.rg Acked-by: Simon Glass <sjg@chromium.org>
* | | kconfig: fix whitespace handling bug of savedefconfigMasahiro Yamada2014-09-16-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ff291f371fa9858426774f3732924bacb61ed1c (kconfig: convert Kconfig helper script into a shell script) introduced another regression. Shell usually handles whitespaces as separators, so "make saveconfig" outputs # CONFIG_FOO is not set into: # CONFIG_FOO is not set Whitespaces should not be treated as separators here. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | kconfig: fix savedefconfig to output empty defconfigMasahiro Yamada2014-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ff291f371fa9858426774f3732924bacb61ed1c (kconfig: convert Kconfig helper script into a shell script) introduced a minor regression. make alldefconfig; make savedefconfig should create an empty 'defconfig'. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | standalone: use GCC_VERSION defined in compiler-gcc.hMasahiro Yamada2014-09-16-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now GCC_VERSION is defined in include/linux/compiler-gcc.h (with a little different definition). Use it and delete the one in examples/standlone/stub.c. This should work on Clang too because __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ are also defined on Clang. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
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