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* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-21-2/+2
| | | | | | | It should be MRC, not MCR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove unused rw-mrc-cache properties in the link and panther dts filesBin Meng2015-10-21-5/+0
| | | | | | | | | "type" and "wipe-value" are never used by the mrccache codes. Remove them to avoid confusion. This also removes the alignment comment in the panther dts file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-21-0/+6
| | | | | | | | | | | | | | | | | | | With MRC cache enabled, when typing 'reset' in the U-Boot shell, BayTrail FSP initialization hangs at "Configuring Memory Start": Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type CurrentMrcData.BootMode = 4 Taking Fastboot path! Configuring Memory Start... Changing reset_cpu() to do a full system reset fixes this issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+15
| | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-21-0/+19
| | | | | | | Save MRC cache to SPI flash in arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()Bin Meng2015-10-21-1/+35
| | | | | | | | | | fsp_init() call has a parameter nvs_buf which is used by FSP as the MRC cache but currently is blindly set to NULL. Retreive the MRC cache from SPI flash and pass it to fsp_init() call. After the call, save FSP produced MRC cache to SPI flash too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-15/+27
| | | | | | | | | | | | | | | | Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-21-108/+4
| | | | | | | | Remove the call to custom mrc cache APIs, and use the ones provided in the mrccache lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add more common routines to manipulate mrc cacheBin Meng2015-10-21-0/+140
| | | | | | | | | | | | | | This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add various minor tidy-ups in mrccache codesBin Meng2015-10-21-18/+16
| | | | | | | | Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Do sanity test on the cache record in mrccache_update()Bin Meng2015-10-21-1/+4
| | | | | | | | For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-21-4/+5
| | | | | | | | mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add ENABLE_MRC_CACHE Kconfig optionBin Meng2015-10-21-0/+8
| | | | | | | Create a Kconfig option for enabling MRC cache. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Add a hdr sub-command to show header informationBin Meng2015-10-21-1/+31
| | | | | | | | It would be helpful to have a command to show FSP header. So far it only supports FSP header which conforms to FSP spec 1.0. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Make hob command a sub-command to fspBin Meng2015-10-21-10/+30
| | | | | | | | | Introduce a new fsp command and make the existing hob command a sub-command to fsp for future extension. Also move cmd_hob.c to the dedicated fsp sub-directory in arch/x86/lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Print GUID whenever applicable in the hob command outputBin Meng2015-10-21-3/+19
| | | | | | | | When examining a HOB, it's useful to see which GUID this HOB belongs to. Add GUID output in the hob command to aid this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Compact the output of hob commandBin Meng2015-10-21-14/+14
| | | | | | | | Compact hob command output, especially by making hob type string a little bit shorter so that we can leave room for future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add SMBIOS table supportBin Meng2015-10-21-2/+522
| | | | | | | | | | | | System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Makefile: Generate U_BOOT_DMI_DATE for SMBIOSBin Meng2015-10-21-0/+2
| | | | | | | | | | | Add U_BOOT_DMI_DATE (format mm/dd/yyyy) generation to be used by SMBIOS tables, as required by SMBIOS spec 3.0 [1]. See chapter 7.1, BIOS information structure offset 08h for details. [1] http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* doc: Complement document about booting VxWorksBin Meng2015-10-21-8/+76
| | | | | | | | Current document about how to boot VxWorks is limited. Add several chapters in README.vxworks to document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* cmd: bootvx: Add asmlinkage to the VxWorks x86 entryBin Meng2015-10-21-0/+6
| | | | | | | | VxWorks on x86 uses stack to pass parameters. Reported-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* cmd: bootvx: Pass E820 information to an x86 VxWorks kernelBin Meng2015-10-21-0/+59
| | | | | | | | | | E820 is critical to the kernel as it provides system memory map information. Pass it to an x86 VxWorks kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
* cmd: bootvx: Always get VxWorks bootline from envBin Meng2015-10-21-85/+68
| | | | | | | | | | | | | | | | | | | So far VxWorks bootline can be contructed from various environment variables, but when these variables do not exist we get these from corresponding config macros. This is not helpful as it requires rebuilding U-Boot, and to make sure these config macros take effect we should not have these environment variables. This is a little bit complex and confusing. Now we change the logic to always contruct the bootline from environments (the only single source), by adding two new variables "bootdev" and "othbootargs", and adding some comments about network related settings mentioning they are optional. The doc about the bootline handling is also updated. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* cmd: bootvx: Pass netmask and gatewayip to VxWorks bootlineBin Meng2015-10-21-2/+15
| | | | | | | | | There are fields in VxWorks bootline for netmask and gatewayip. We can get these from U-Boot environment variables and pass them to VxWorks, just like ipaddr and serverip. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cmd: bootvx: Avoid strlen() calls when constructing VxWorks bootlineBin Meng2015-10-21-10/+10
| | | | | | | | Remember the position in the VxWorks bootline buffer to avoid the call to strlen() each time. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cmd: elf: Reorder load_elf_image_phdr() and load_elf_image_shdr()Bin Meng2015-10-21-82/+79
| | | | | | | | Move load_elf_image_phdr() and load_elf_image_shdr() to the beginning of the cmd_elf.c so that forward declaration is not needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* cmd: Clean up cmd_elf a little bitBin Meng2015-10-21-98/+73
| | | | | | | | | This commit cleans up cmd_elf.c per U-Boot coding convention, and removes the unnecessary DECLARE_GLOBAL_DATA_PTR and out-of-date powerpc comments (it actually supports not only powerpc targets). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* cmd: Convert CONFIG_CMD_ELF to KconfigBin Meng2015-10-21-118/+33
| | | | | | Convert CONFIG_CMD_ELF to Kconfig and tidy up affected boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove quotation mark in CONFIG_HOSTNAMEBin Meng2015-10-21-1/+1
| | | | | | | | CONFIG_HOSTNAME is an environment varible, so that quotation mark is not needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move install_e820_map() out of zimage.cBin Meng2015-10-21-29/+41
| | | | | | | | install_e820_map() has nothing to do with zimage related codes. Move it to a dedicated place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Initialize GDT entry 1 to be the 32-bit CS as wellBin Meng2015-10-21-1/+6
| | | | | | | | Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-21-0/+33
| | | | | | | | | | Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-21-32/+0
| | | | | | | Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Enable VGA address forwarding on bridgesBin Meng2015-10-21-0/+18
| | | | | | | | | To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Fix pci_last_busno() to return the real last bus noBin Meng2015-10-21-24/+1
| | | | | | | | | Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* video: vesa_fb: Fix wrong return value check of pci_find_class()Bin Meng2015-10-21-1/+1
| | | | | | | | | When pci_find_class() fails to find a device, it returns -ENODEV. But now we check the return value against -1. Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* pci: Set PCI_COMMAND_IO bit for VGA deviceBin Meng2015-10-21-0/+6
| | | | | | | | PCI_COMMAND_IO bit must be set for VGA device as it needs to respond to legacy VGA IO address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Adjust pci_find_and_bind_driver() to return -EPERMSimon Glass2015-10-21-12/+19
| | | | | | | | | | | | | | The current code returns 0 even if it failed to find or bind a driver. The caller then has to check the returned device to see if it is NULL. It is better to return an error code in this case so that it is clear what happened. Adjust the code to return -EPERM, indicating that the device was not bound because it is not needed for pre-relocation use. Add comments so that the return value is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct a few debug() statementsSimon Glass2015-10-21-2/+2
| | | | | | | | One debug() statement is missing a newline. The other has a repeated word. Fix these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Tidy up auto-config error handlingSimon Glass2015-10-21-3/+12
| | | | | | | | | | | When the auto-configuration process fails for a device (generally due to lack of memory) we should return the error correctly so that we don't continue to try memory allocations which will fail. Adjust the code to check for errors and abort if something goes wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* malloc_simple: Add debug() informationSimon Glass2015-10-21-0/+4
| | | | | | | | | It's useful to get a a trace of memory allocations in early init. Add a debug() call to provide that. It can be enabled by adding '#define DEBUG' to the top of the file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Prepare v2015.10Tom Rini2015-10-19-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* powerpc: Drop old non-generic-board codeSimon Glass2015-10-19-986/+0
| | | | | | This code is no-longer used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARDPaul Gortmaker2015-10-19-0/+2
| | | | Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* sbc8641d: increase monitor size from 256k to 384kPaul Gortmaker2015-10-19-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Between v2015.07-rc1 and v2015.07-rc2 this board started silent boot failure. A bisect led to commit 6eed3786c68c8a49d ("net: Move the CMD_NET config to defconfigs"). This commit looks harmless in itself, but it did implicitly add a feature to the image which led to this: u-boot$git describe 6eed3786c68c8a49d v2015.07-rc1-412-g6eed3786c68c ^^^ u-boot$ls -l ../41*/u-boot.bin -rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin -rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin u-boot$bc bc 1.06.95 Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc. This is free software with ABSOLUTELY NO WARRANTY. For details type `warranty'. 256*1024 262144 i.e. we finally broke through the 256k monitor size. Jump it up to 384k and fix the hard coded value used in the env offset at the same time. We were probably flirting with the 256k size issue without knowing it when testing on different baselines in earlier commits, but since this is all board specific, a rebase or reorder to put this commit 1st is of little value. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* sbc8641d: add basic flash setup instructions to README filePaul Gortmaker2015-10-19-0/+21
| | | | | | | ...so that I don't have to go work them out from scratch again by peering at the manual. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* sbc8641d: set proper environment sector size.Paul Gortmaker2015-10-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When debugging an env fail due to too small a malloc pool, it was noted that the env write was 256k. But the device sector size is 1/2 that, as can be seen from "fli" output: Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 131 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 64 bytes Sector Start Addresses: FF000000 E RO FF020000 E RO FF040000 E RO FF060000 E RO FF080000 E RO FF0A0000 E RO FF0C0000 E RO FF0E0000 E RO FF100000 E RO FF120000 E RO [...] FFF00000 RO FFF20000 RO FFF40000 RO FFF60000 RO FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 E RO FFFE8000 RO FFFF0000 E RO FFFF8000 RO => The desired env sector is FFF40000->FFF60000, or 0x20000 in length, just after the 256k u-boot image which starts @ FFF00000. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* sbc8641d: increase malloc pool size to a sane defaultPaul Gortmaker2015-10-19-1/+1
| | | | | | | | | | | | Currently the board fails to save its env, since the env size is much smaller than the sector size, and the malloc fails for the pad buffer, giving the user visible symptom of: Unable to save the rest of sector (253952) Allow for 1M malloc pool, the same as used on the sbc8548 board. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* sbc8641d: enable command line editingPaul Gortmaker2015-10-19-0/+1
| | | | | | It is just too painful to use interactively without it. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* image-fit: Fix signature checkingAndrej Rosano2015-10-19-1/+3
| | | | | | | On signature verification failures fit_image_verify() should exit with error. Signed-off-by: Andrej Rosano <andrej@inversepath.com>
generated by cgit v1.1 at 2024-11-10 04:24:50 +0000