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| * | | i.MX28: Improve passing of data from SPL to U-BootMarek Vasut2012-05-15-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass memory size from SPL via structure located in SRAM instead of SCRATCH registers. This allows passing more data about boot from SPL to U-Boot, like the boot mode pads configuration. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | M28EVK: Add SD update commandMarek Vasut2012-05-15-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "update_sd_firmware" command to easily reload the SD card of m28evk kit. This comes handy when the board boots from SD card. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | M28EVK: Implement support for new board V2.0Marek Vasut2012-05-15-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | FEC: Abstract out register setupMarek Vasut2012-05-15-46/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Abstract out common register setup. This also configured r_cntrl to correct value at registration time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchangedStefano Babic2012-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After an update to the MX51 reference manual (Rev. 5), the values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH are now clearly wrong: "Bit 13: High / Low Output Voltage Range. This bit selects the output voltage mode for SD2_CMD. 0 High output voltage mode 1 Low output voltage mode" The values are currently negated in code - fixed. Reported-by: David Jander <david.jander@protonic.nl> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: David Jander <david.jander@protonic.nl> Acked-by: David Jander <david.jander@protonic.nl> Acked-by: Marek Vasut <marek.vasut@gmail.com>
| * | | i.MX28: Add delay after CPU bypass is clearedMarek Vasut2012-05-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
| * | | spi: mxs: Allow other chip selects to workFabio Estevam2012-05-15-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2. Currently only SS0 is supported in the mxs_spi driver. Allow all the three chip select to work by selecting the desired one in bits 20 and 21 of the HW_SSP_CTRL0 register. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | spi: mxs: Introduce spi_cs_is_valid()Fabio Estevam2012-05-15-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce spi_cs_is_valid() for validating spi bus and chip select numbers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | | mx53loco: Remove unneeded gpio_set_value()Fabio Estevam2012-05-15-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to set the VBUS power enable to 0 first and then to 1. Set it to 1 in the gpio_direction_output() function. While at it, use the standard naming convention for the GPIO comment. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx53loco: Add CONFIG_REVISION_TAGFabio Estevam2012-05-15-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx53loco: Turn on VUSB regulatorFabio Estevam2012-05-15-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator so that the mx53 USBH1 PHY receives the 3.3V voltage. Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the commands: usb start usb info ,which correctly detected and printed the USB pen drive information. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx53loco: Add mc34708 support and set mx53 frequency at 1GHzFabio Estevam2012-05-15-12/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | pmic: dialog: Avoid name conflictsFabio Estevam2012-05-15-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC, we need to be able to build both drivers. Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | imx: Add u-boot.imx as target for ARM9 i.MX SOCsTimo Ketola2012-05-15-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX2: Include asm/types.h in arch-mx25/imx-regs.hTimo Ketola2012-05-15-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | types.h must be included in imx-regs.h if one wants to include imx-regs.h in a board configuration file. That for one's part is necessary, if one wants to use addresses defined in imx-regs.h. For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and a proper thing is to define it with IMX_MMC_SDHCx_BASE in board configuration file. This patch fixes the build in that case. Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | imx: usb: There is no such registerTimo Ketola2012-05-15-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero). Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX25: usb: Set PORTSCx registerTimo Ketola2012-05-15-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controller in i.MX25 has a PORTSCx registers which should be set. In this regard it is similar to the controller in i.MX31. As this file is compiled only with i.MX25 and -31, #ifdef check can be removed. Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | imx: nand: Support flash based BBTTimo Ketola2012-05-15-0/+33
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | i.MX25: This architecture has a GPIO4 tooTimo Ketola2012-05-15-1/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX25: esdhc: Add mxc_get_clock infrastructureTimo Ketola2012-05-15-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere. Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX6: mx6q_sabrelite: add SATA bindingsEric Nelson2012-05-15-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: stefano Babic <sbabic@denx.de>
| * | | i.MX6: add enable_sata_clock()Eric Nelson2012-05-15-0/+152
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX6: Add ANATOP regulator initDirk Behme2012-05-15-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com>
| * | | mx28evk: add NAND supportLauri Hintsala2012-05-15-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND support is not enabled by default because Eval Kit is not delivered with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config. Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | USB: ehci-mx6: Fix broken IO accessWolfgang Grandegger2012-05-15-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get USB working again on the i.MX6, this patch fixes a bug introduced with commit 522b2a0 "Add proper IO accessors for mx6 usb registers.". At that occasion, I also added the missing __iomem directive. Cc: Marek Vasut <marex@denx.de> CC: Fabio Estevam <festevam@gmail.com> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * | | M28: Scan only first 512 MB of DRAM to avoid memory wraparoundMarek Vasut2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
| * | | Revert "i.MX28: Enable additional DRAM address bits"Marek Vasut2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a. Apparently, this commit got mainline only because of out-of-tree port and causes breakage on board that is mainline. Revert. Reason: * The OOT board has 512MB of DRAM, enabling this additional address line enabled it to work fine with 512MB of RAM. * Every mainline port has max. 256MB of DRAM, therefore this revert has no impact on any mainline port * Though this caused a problem with new M28 board with 256MB of DRAM where the chips are wired differently. The patch-to-be-reverted caused the DRAM to behave like this: [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again] Therefore to retain the current one-memory-init-rules-them-all situation, revert this patch until another board emerges and will actually be pushed mainline that needs different setup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
| * | | M28: Enable FDT supportMarek Vasut2012-05-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will eventually be needed with Linux 3.5, which will be the point when MXS will be switched to FDT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
| * | | mx53loco: Add support for 1GHz operation for DA9053-based boardsFabio Estevam2012-05-15-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two types of mx53loco boards: initial boards were built with a Dialog DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC. Add DA9053 PMIC support and adjust the required voltages and clocks for running the CPU at 1GHz. Tested on both versions of mx53loco boards. In the case of a MC34708-based board the CPU operating voltage remains at 800MHz. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by : Stefano Babic <sbabic@denx.de>
| * | | mx53loco: Allow to print CPU information at a later stageFabio Estevam2012-05-15-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print CPU information within board_late_init(). This is in preparation for adding 1GHz support, which requires programming a PMIC via I2C. As I2C is only available after relocation, print the CPU information later at board_late_init(), so that the CPU frequency can be printed correctly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx5: Add clock config interfaceFabio Estevam2012-05-15-5/+454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx5: Add clock config interface Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | imx-common: Factor out get_ahb_clk()Fabio Estevam2012-05-15-34/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_ahb_clk() is a common function between mx5 and mx6. Place it into imx-common directory. Cc: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flowEric Nelson2012-05-15-2/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uses the 'magic_keys' idiom as described in doc/README.kbd: http://lists.denx.de/pipermail/u-boot/2012-April/122502.html Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx31pdk: Allow booting a zImage kernelFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Allow booting a zImage kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6qarm2: Allow booting a zImage kernelFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow booting a zImage kernel. Cc: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com>
| * | | mx6qsabrelite: Allow booting a zImage kernelFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow booting a zImage kernel. Cc: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx28evk: Allow booting a zImage kernelFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Allow booting a zImage kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | m28evk: Allow to booting a dt kernelFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Allow to booting a dt kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx28evk: Allow to booting a dt kernelFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Allow to booting a dt kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6qsabrelite: No need to set the direction for GPIO3_23 againFabio Estevam2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a 'gpio_direction_output(87, 0);' call previously, so the GPIO direction is already established. Use gpio_set_value() for changing the GPIO output then. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@googlemail.com>
| * | | pmic: Add support for the Dialog DA9053 PMICFabio Estevam2012-05-15-0/+225
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the Dialog DA9053 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | MX53: mx53loco: Add SATA supportStefano Babic2012-05-15-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org>
| * | | MX53: Add support to ESG ima3 boardStefano Babic2012-05-15-0/+721
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ESG ima3-mx53 board is based on the Freescale i.MX53 SOC. It boots from NOR (128 MB) and supports Ethernet (FEC), SATA. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | SATA: add driver for MX5 / MX6 SOCsStefano Babic2012-05-15-2/+1308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is part of Freescale's LTIB for MX5 / MX6. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Terry Lv <r65388@freescale.com> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com>
| * | | MX53: add function to set SATA clock to internalStefano Babic2012-05-15-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX53 SATA interface can use an internal clock (USB PHY1) instead of an external clock. This is an undocumented feature, but used on most Freescale's evaluation boards, such as MX53-loco. As stated by Freescale's support: Fuses (but not pins) may be used to configure SATA clocks. Particularly the i.MX53 Fuse_Map contains the next information about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) '00' - 100MHz (External) '01' - 50MHz (External) '10' - 120MHz, internal (USB PHY) '11' - Reserved Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * | | SATA: check for return value from sata functionsStefano Babic2012-05-15-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sata functions are called even if previous functions failed because return value is not checked. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Dirk Behme <dirk.behme@de.bosch.com> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * | | MX5: Add definitions for SATA controllerStefano Babic2012-05-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com>
| * | | NET: fec_mxc.c: Add a way to disable auto negotiationStefano Babic2012-05-15-1/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * | | Define UART4 and UART5 base addressesStefano Babic2012-05-15-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | EXYNOS: Change bits per pixel value proper for u-boot.Donghwa Lee2012-05-15-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vl_bpix of vidinfo_t was changed proper value for u-boot. It is used to multiple of 2 by using NBITS() macro. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-11-08 09:48:50 +0000