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| * | | arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xxMatt Porter2012-05-15-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com>
| * | | OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device TreeJon Hunter2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For OMAP4 boards, such as the panda-es, that have 1GB of memory the linux kernel fails to locate the device tree blob on boot. The reason being is that u-boot is copying the DT blob to the upper part of RAM when booting the kernel and the kernel is unable to access the blob. By setting the fdt_high variable to either 0xffffffff (to prevent the copy) or 0xac000000 (704MB boundary of memory for OMAP4) the kernel is able to locate the DT blob and boot. Based upon following patch by Dirk Behme set the fdt_high variable to allow booting with device tree on OMAP4 boards. "7e9603e i.mx6q: configs: Add fdt_high and initrd_high variables" Cc: Sricharan R <r.sricharan@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
| * | | omap4: do not enable auxiliary coresTero Kristo2012-05-15-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting up these cores (dsp / ivahd / cortex-m3) is bad without firmware running on them, and they will hang preventing any kind of sleep transitions later on with the kernel. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: R Sricharan <r.sricharan@ti.com>
| * | | omap4: do not enable fs-usb moduleTero Kristo2012-05-15-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If this is done in the bootloader, the FS-USB will later be stuck into intransition state, which will prevent the device from entering idle. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * | | omap4: panda: disable uart2 pads during bootTero Kristo2012-05-15-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If uart2 is enabled during boot, spurious wifi chip transmission will hang the module and it is impossible to recover from this situation without hard reset. This will prevent any l4_per domain idle transitions. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * | | igep00x0: change mpurate from 500 to autoEnric Balletbo i Serra2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the default mpurate variable from 500 to auto on all IGEP boards, with this the default rate is autoselected. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | igep00x0: enable the use of a plain text fileEnric Balletbo i Serra2012-05-15-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on commit cf073e49bc3502be1b48a0e3faf0cde9edbb89db for beagleboard Using the new env import command it is possible to use plain text files instead of script-images. Plain text files are much easier to handle. E.g. If your boot.scr contains the following: ----------------------------------- setenv dvimode 1024x768-16@60 run loaduimage run mmcboot ----------------------------------- you could create a file named uEnv.txt and use that instead of boot.scr: ----------------------------------- dvimode=1024x768-16@60 uenvcmd=run loaduimage; run mmcboot ----------------------------------- The variable uenvcmd (if existent) will be executed (using run) after uEnv.txt was loaded. If uenvcmd doesn't exist the default boot sequence will be started, therefore you could just use ----------------------------------- dvimode=1024x768-16@60 ----------------------------------- as uEnv.txt because loaduimage and mmcboot is part of the default boot sequence Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | tegra2: trivially enable 13 mhz crystal frequencyLucas Stach2012-05-15-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed for upcoming Toradex Colibri T20 upstream support. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Enable keyboard for SeaboardSimon Glass2012-05-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the standard keyboard on Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Switch on console mux and use environment for consoleSimon Glass2012-05-15-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All tegra boards will use these options by default. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add tegra keyboard driverRakesh Iyer2012-05-15-0/+410
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for internal matrix keyboard controller for Nvidia Tegra platforms. This driver uses the fdt decode function to obtain its key codes. Support for the Ctrl modifier is provided. The left and right ctrl keys are dealt with in the same way. This uses the new keyboard input library (drivers/input/input.c) to decode keys and handle most of the common input logic. The new key matrix library is also used to decode (row, column) key positions into key codes. The intent is to make this driver purely about dealing with the hardware. Key detection before the driver is loaded is supported. This key will be picked up when the keyboard driver is initialized. Modified by Bernie Thompson <bhthompson@chromium.org> and Simon Glass <sjg@chromium.org> for device tree, input layer, key matrix and various other things. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: fdt: Add keyboard definitions for SeaboardAnton Staff2012-05-15-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seaboard uses a QUERTY keyboard. We add key codes for this to enable key scanning to work. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: fdt: Add keyboard controller definitionAnton Staff2012-05-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra keyboard controller provides a simple interface to a matrix keyboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add keyboard support to funcmuxSimon Glass2012-05-15-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add funcmux support for the default keyboard mapping. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | input: Add support for keyboard matrix decoding from an fdtBernie Thompson2012-05-15-0/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Matrix keyboards require a key map to be set up, and must also deal with key ghosting. Create a keyboard matrix management implementation which can be leveraged by various keyboard drivers. This includes code to read the keymap from the FDT and perform debouncing. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | input: Add generic keyboard input handlerSimon Glass2012-05-15-0/+578
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a module which understands converting key codes (or scan codes) to ASCII characters. It includes FIFO support and can call back to drivers to read new characters when its FIFO is empty. Keycode maps are provided for un-modified, shift and ctrl keys. The plan is to use this module where such mapping is required. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | input: Add linux/input.h for key code supportSimon Glass2012-05-15-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to able to decode Linux fdt keymaps, so bring part of this enormous header file over to U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | fdt: Add fdtdec functions to read byte arrayAnton Staff2012-05-15-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes we don't need a full cell for each value. This provides a simple function to read a byte array, both with and without copying it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Enable LP0 on SeaboardSimon Glass2012-05-15-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables LP0 to support suspend / resume on Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: fdt: Add EMC data for Tegra2 SeaboardSimon Glass2012-05-15-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds timings for T20 and T25 Seaboards, using the bindings found here: http://patchwork.ozlabs.org/patch/132928/ We supply both full speed options for normal running, and half speed options for testing / development. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: i2c: Add function to find DVC busSimon Glass2012-05-15-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus. This allows us to talk to the PMU. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | fdt: tegra: Add EMC node to device treeSimon Glass2012-05-15-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a definition of the memory controller node according to the bindings here: http://patchwork.ozlabs.org/patch/132928/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add EMC settings for SeaboardJimmy Zhang2012-05-15-2/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Turn off power detect in board initWei Ni2012-05-15-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra core power rail has leakage voltage around 0.2V while system in suspend mode. The source of the leakage should be coming from PMC power detect logic for IO rails power detection. That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0' to PWR_DET (APBDEV_PMC_PWR_DET_0). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Set up warmboot code on Nvidia boardsSimon Glass2012-05-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Call the function to put warmboot boot in a suitable place for resume. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Setup PMC scratch info from ap20 setupYen Lin2012-05-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Save SDRAM parameters into the warmboot scratch registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add warmboot implementationYen Lin2012-05-15-0/+869
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to set up the warm boot area in the Tegra CPU ready for a resume after suspend. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Set up PMU for Nvidia boardsSimon Glass2012-05-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust PMU to permit maximum frequency operation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add PMU to manage power suppliesJimmy Zhang2012-05-15-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power supplies must be adjusted in line with clock frequency. This code provides a simple routine to set the voltage to allow operation at maximum frequency. - Split PMU code into separate TPS6586X driver Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add EMC support for optimal memory timingsJimmy Zhang2012-05-15-0/+404
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for setting up the memory controller parameters. Boards can set up an appropriate table in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add header file for APB_MISC registerSimon Glass2012-05-15-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a basic header file for this register, to be filled in as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add tegra_get_chip_type() to detect SKUSimon Glass2012-05-15-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to know which type of chip we are running on - the Tegra family has several SKUs. This can be determined by reading a fuse register, so add this function to ap20. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add flow, gp_padctl, fuse, sdram headersYen Lin2012-05-15-0/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These headers provide access to additional Tegra features. flow - start/stop CPUs sdram - parameters for SDRAM fuse - access to on-chip fuses / security settings gp_padctl - pad control and general purpose registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add crypto library for warmboot codeYen Lin2012-05-15-0/+266
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides an interface to aes.c for the warmboot code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add functions to access low-level Osc/PLL detailsSimon Glass2012-05-15-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass() to find out if the Oscillator is bypassed. These are needed by warmboot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Move ap20.h header into arch locationSimon Glass2012-05-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to include this from board code, so move the header into an easily-accessible location. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Add AES crypto libraryYen Lin2012-05-15-0/+669
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for AES using an implementation from Karl Malbrain. This offers small code size (around 5KB on ARM) and supports 128-bit AES only. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | i2c: Add TPS6586X driverSimon Glass2012-05-15-0/+349
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This power management chip supports battery charging and a large number of power supplies. This initial driver only provides the ability to adjust the two synchronous buck converters SM0 and SM1 in a stepwise manner. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Add abs() macro to return absolute valueSimon Glass2012-05-15-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This macro is generally useful to make it available in common. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | | fdt: Add function to return next compatible subnodeSimon Glass2012-05-15-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to iterate through subnodes of a parent, looking only at compatible nodes. Add a utility function to do this for us. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | fdt: Add function to locate an array in the device treeSimon Glass2012-05-15-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdtdec_locate_array() locates an integer array but does not copy it. This saves the caller having to allocated wasted space. Access to array elements should be through the fdt32_to_cpu() macro. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | i.MX28: Avoid redefining serial_put[cs]()Marek Vasut2012-05-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not define serial_putc() and serial_puts() calls if CONFIG_SPL_SERIAL_SUPPORT is set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX28: Check if WP detection is implemented at allMarek Vasut2012-05-15-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the WP function is NULL, simply assume the card is always RW. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | i.MX28: Add battery boot components to SPLMarek Vasut2012-05-15-8/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | i.MX28: Reorder battery status functions in SPLMarek Vasut2012-05-15-64/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | i.MX28: Add LRADC init to i.MX28 SPLMarek Vasut2012-05-15-1/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is part of battery boot support for i.MX28. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | i.MX28: Add LRADC register definitionsMarek Vasut2012-05-15-0/+401
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | i.MX28: Shut down the LCD controller before resetMarek Vasut2012-05-15-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF data pins interferes with the BootROM's boot mode sampling. So shut the controller down. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | i.MX28: Add LCDIF register definitionsMarek Vasut2012-05-15-0/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | | i.MX28: Implement boot pads sampling and reportingMarek Vasut2012-05-15-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements code that samples i.MX28 boot pads and reports boot mode accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
generated by cgit v1.1 at 2024-11-08 07:38:48 +0000