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* sandbox: Add dummy SATA functionsSimon Glass2016-05-17-1/+34
| | | | | | | Add some functions needed by the SATA code. This allows it to be compiled for sandbox, thus increasing build coverage. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add dummy SCSI functionsSimon Glass2016-05-17-1/+30
| | | | | | | Add some functions needed by the SCSI code. This allows it to be compiled for sandbox, thus increasing build coverage. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add string and 16-bit I/O functionsSimon Glass2016-05-17-0/+15
| | | | | | | | | | Add outsw() and insw() functions for sandbox, as these are needed by the IDE code. The functions will not do anything useful if called, but allow the code to be compiled. Also add out16() and in16(), required by systemace. Signed-off-by: Simon Glass <sjg@chromium.org>
* Allow iotrace byte access to use an address of any sizeSimon Glass2016-05-17-2/+3
| | | | | | | | If an address is used with readb() and writeb() which is smaller than the expected size (e.g. 32-bit value on a machine with 64-bit addresses), a warning results. Fix this by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Rename disk uclass to ahciSimon Glass2016-05-17-12/+14
| | | | | | | | This started as 'ahci' and was renamed to 'disk' during code review. But it seems that this is too generic. Now that we have a 'blk' uclass, we can use that as the generic piece, and revert to ahci for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Drop CONFIG_SYS_SCSI_SCAN_BUS_REVERSESimon Glass2016-05-17-8/+0
| | | | | | | This option is not used by any board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: sandbox: Add a board for sandbox without CONFIG_BLKSimon Glass2016-05-17-0/+175
| | | | | | | | While the driver-model block device support is in progress, it is useful to build sandbox both with and without CONFIG_BLK. Add a separate board for the latter. Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "dm: sandbox: Drop the pre-DM host implementation"Simon Glass2016-05-17-0/+90
| | | | | | | | | | Bring this support back so that sandbox can be compiled with CONFIG_BLK. This allows sandbox to have greater build coverage during the block-device transition. This can be removed again later. This reverts commit 33cf727b1634dbd9cd68a6ebc444a88f053822d7. Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: exynos(s5p): remove gpio_xlate routineEric Nelson2016-05-17-11/+0
| | | | | | | | | With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass, the Exynos/S5P gpio driver doesn't need a custom xlate routine. Signed-off-by: Eric Nelson <eric@nelint.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* gpio: rk: remove gpio_xlate routineEric Nelson2016-05-17-11/+0
| | | | | | | | With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass, the Rockchip gpio driver doesn't need a custom xlate routine. Signed-off-by: Eric Nelson <eric@nelint.com> Acked-by: Simon Glass <sjg@chromium.org>
* gpio: pic32: remove gpio_xlate routineEric Nelson2016-05-17-10/+0
| | | | | | | | | With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass, the pic32 gpio driver doesn't need a custom xlate routine. Signed-off-by: Eric Nelson <eric@nelint.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* gpio: omap: remove gpio_xlate routineEric Nelson2016-05-17-11/+0
| | | | | | | | With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass, the omap gpio driver doesn't need a custom xlate routine. Signed-off-by: Eric Nelson <eric@nelint.com> Acked-by: Simon Glass <sjg@chromium.org>
* gpio: intel_broadwell: remove gpio_xlate routineEric Nelson2016-05-17-10/+0
| | | | | | | | With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass, the intel_broadwell driver doesn't need a custom xlate routine. Signed-off-by: Eric Nelson <eric@nelint.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: gpio: add a default gpio xlate routineEric Nelson2016-05-17-12/+37
| | | | | | | | | | | | | | | | | Many drivers use a common form of offset + flags for device tree nodes. e.g.: <&gpio1 2 GPIO_ACTIVE_LOW> This patch adds a common implementation of this type of parsing and calls it when a gpio driver doesn't supply its' own xlate routine. This will allow removal of the driver-specific versions in a handful of drivers and simplify the addition of new drivers. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: usb: common: add common code for usb drivers to useMugunthan V N2016-05-17-0/+50
| | | | | | | Add common usb code which usb drivers makes use of it. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: gpio: introduce 74x164 driverPeng Fan2016-05-17-0/+202
| | | | | | | | | | | | | | | | | | | | Introduce driver to support "fairchild,74hc595" devices. 1. Take linux drivers/drivers/gpio/gpio-74x164.c as reference. 2. Following the naming used in Linux driver with gen_7x164 as the prefix. 3. Enable CONFIG_DM_74X164 to use this driver. 4. Follow Documentation/devicetree/bindings/gpio/gpio-74x164.txt to add device nodes 5. Tested on i.MX6 UltraLite with 74LV595 using gpio command and oscillograph. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Chin Liang See <clsee@altera.com> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: spi: introduce dm apiPeng Fan2016-05-17-7/+73
| | | | | | | | | | | Introduce dm_spi_claim_bus, dm_spi_release_bus and dm_spi_xfer Convert spi_claim_bus, spi_release_bus and spi_xfer to use the new API. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: spi: soft_spi: switch to use linux compatible stringPeng Fan2016-05-17-15/+33
| | | | | | | | | | | | | | 1. Support compatible string "spi-gpio" which is used by Linux Linux use different bindings, so use UBOOT_COMPAT and LINUX_COMPAT to differentiate them. 2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle no rx or no tx case. 3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: spi: soft_spi bug fixPeng Fan2016-05-17-7/+12
| | | | | | | | | | | When doing xfer, should use device->parent, but not device When doing bit xfer, should use "!!(tmpdout & 0x80)", but not "(tmpdout & 0x80)" Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fdt: fix dev_get_addr_name node offsetStephen Warren2016-05-17-2/+2
| | | | | | | | Use the device's own DT offset, not the device's parent's. Fixes: 43c4d44e3330 ("fdt: implement dev_get_addr_name()") Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* video: tegra: refuse to bind to disabled dcsStephen Warren2016-05-17-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents the following boot-time message on any board where only the first DC is in use, yet the DC's DT node is enabled: stdio_add_devices: Video device failed (ret=-22) (This happens on at least Harmony, Ventana, and likely any other Tegra20 board with display enabled other than Seaboard). The Tegra DC's DT node represents a display controller. It may itself drive an integrated RGB display output, or be used by some other display controller such as HDMI. For this reason the DC node itself is not enabled/disabled in DT; the DC itself is considered a shared resource, not the final (board-specific) display output. The node should instantiate a display output driver only if the rgb subnode is enabled. Other output drivers are free to use the DC if they are enabled and their DT node references the DC's DT node. Adapt the Tegra display drivers' bind() routine to only bind to the DC's DT node if the RGB subnode is enabled. Now that the display driver does the right thing, remove the workaround for this issue from Seaboard's DT file. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: allow drivers to refuse to bindStephen Warren2016-05-17-0/+4
| | | | | | | | | | | | | In some cases, drivers may not want to bind to a device. Allow bind() to return -ENODEV in this case, and don't treat this as an error. This can be useful in situations where some information source other than the DT node's main status property indicates whether the device should be enabled, for example other DT properties might indicate this, or the driver might query non-DT sources such as system fuses or a version number register. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* buildman: allow more incremental buildingStephen Warren2016-05-17-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One use-case for buildman is to continually run it interactively after each small step in a large refactoring operation. This gives more immediate feedback than making a number of commits and then going back and testing them. For this to work well, buildman needs to be extremely fast. At present, a couple issues prevent it being as fast as it could be: 1) Each time buildman runs "make %_defconfig", it runs "make mrproper" first. This throws away all previous build results, requiring a from-scratch build. Optionally avoiding this would speed up the build, at the cost of potentially causing or missing some build issues. 2) A build tree is created per thread rather than per board. When a thread switches between building different boards, this often causes many files to be rebuilt due to changing config options. Using a separate build tree for each board would avoid this. This does put more strain on the system's disk cache, but it is worth it on my system at least. This commit adds two command-line options to implement the changes described above; -I ("--incremental") turns of "make mrproper" and -P ("--per-board-out-dir") creats a build directory per board rather than per thread. Tested: ./tools/buildman/buildman.py tegra ./tools/buildman/buildman.py -I -P tegra ./tools/buildman/buildman.py -b tegra_dev tegra ./tools/buildman/buildman.py -b tegra_dev -I -P tegra ... each once after deleting the buildman result/work directory, and once "incrementally" after a previous identical invocation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org> # v1 Tested-by: Simon Glass <sjg@chromium.org> # v1 Acked-by: Simon Glass <sjg@chromium.org>
* m68k: add DM model serial driverangelo@sysam.it2016-05-17-44/+167
| | | | | | | | Boards can now use DM serial driver, or still legacy mcf uart driver version. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Simon Glass <sjg@chromium.org>
* m68k: add malloc memory for early mallocangelo@sysam.it2016-05-17-39/+147
| | | | | | | | | To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used. So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and call to board_init_f_mem() is added for all cpu's. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Simon Glass <sjg@chromium.org>
* dm: gpio: pca953x: introduce driver model support for pca953xPeng Fan2016-05-17-0/+375
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new driver that supports driver model for pca953x. The pca953x chips are used as I2C I/O expanders. This driver is designed to support the following chips: " 4 bits: pca9536, pca9537 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, pca9556, pca9557, pca9574, tca6408, xra1202 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, tca6416 24 bits: tca6424 40 bits: pca9505, pca9698 " But for now this driver only supports max 24 bits and pca953x compatible chips. pca957x compatible chips are not supported now. These can be addressed when we need to add such support for the different chips. This driver has been tested on i.MX6 SoloX Sabreauto board with max7310 i2c expander using gpio command as following: =>gpio status -a Bank gpio@30_: gpio@30_0: input: 1 [ ] => dm tree: i2c [ ] | | `-- i2c@021a8000 gpio [ ] | | |-- gpio@30 gpio [ ] | | `-- gpio@32 Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: Andrea Scian <andrea.scian@dave.eu> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Michal Simek <michal.simek@xilinx.com> #on ZynqMP zcu102
* Prepare v2016.05Tom Rini2016-05-16-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* sunxi: Enable USB host in CHIP defconfigHans de Goede2016-05-15-0/+1
| | | | | | Reported-and-tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* test, tools: update tbot documentationHeiko Schocher2016-05-13-153/+103
| | | | | | | | update tbot documentation in U-Boot, as I just merged the event system into tbots master branch. Signed-off-by: Heiko Schocher <hs@denx.de>
* tests: py: fix NameError exception if bdi cmd is not supportedHeiko Schocher2016-05-13-0/+1
| | | | | | | | | | | | test/py raises an error, if a board has not enabled bdi command > pytest.skip('bdinfo command not supported') E NameError: global name 'pytest' is not defined import pytest in test/py/u_boot_utils.py fixes this. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-12-21/+46
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* arm: socfpga: Update iomux and pll for c5 socdk RevEDinh Nguyen2016-05-10-36/+36
| | | | | | Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* warp7: Fix boot by selecting CONFIG_OF_LIBFDTFabio Estevam2016-05-10-0/+1
| | | | | | | | | | | | | | | | CONFIG_OF_LIBFDT needs to be selected to avoid the following boot problem: reading zImage 6346216 bytes read in 118 ms (51.3 MiB/s) Booting from mmc ... reading imx7d-warp.dtb 32593 bytes read in 11 ms (2.8 MiB/s) Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ] FDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ### Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-05-06-168/+90
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| * socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabledAnatolij Gustschin2016-05-06-1/+1
| | | | | | | | | | | | | | Building without ethernet driver doesn't work. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * mtd: cqspi: Simplify indirect read codeMarek Vasut2016-05-06-71/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The indirect read code is a pile of nastiness. This patch replaces the whole unmaintainable indirect read implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. All the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. There is no speed change of the read operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
| * mtd: cqspi: Simplify indirect write codeMarek Vasut2016-05-06-96/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The indirect write code is buggy pile of nastiness which fails horribly when the system runs fast enough to saturate the controller. The failure results in some pages (256B) not being written to the flash. This can be observed on systems which run with Dcache enabled and L2 cache enabled, like the Altera SoCFPGA. This patch replaces the whole unmaintainable indirect write implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. While this makes the patch look terrifying and violates all best-practices of software development, all the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
| * arm: socfpga: socrates: Add 'time' commandStefan Roese2016-05-06-0/+1
| | | | | | | | | | | | | | | | The time command is very helpful for performance and regressions tests. So lets enable it on SoCrates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
| * ARM: socfpga: Disable USB OC protection on SoCratesMarek Vasut2016-05-06-0/+1
| | | | | | | | | | | | | | | | This is mandatory, otherwise the USB does not work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-05-06-13/+36
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| * | usb: gadget: dfu: discard dead codePeng Fan2016-05-06-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported by Coverity: Logically dead code (DEADCODE) dead_error_line: Execution cannot reach this statement: (f_dfu->strings + --i).s = .... If calloc failed, i is still 0 and no need to call free, so discard the dead code. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | dfu: avoid memory leakPeng Fan2016-05-06-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: dwc2: Add delay to fix the USB detection problem on SoCFPGAStefan Roese2016-05-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With patch c998da0d (usb: Change power-on / scanning timeout handling), the USB scanning is started earlier and with a smaller timeout. This resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not getting detected any more. This patch now adds a 1 second delay (in the host mode only) to the DWC2 driver before the scanning is started. With this delay, now all problematic USB keys are detected successfully again. And there is no need any more to change the delay / timeout in the common USB code (usb_hub.c). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: hub: Don't continue on get_port_status failureMarek Vasut2016-05-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code shouldn't continue probing the port if get_port_status() failed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: Assure Get Descriptor request is in separate microframeMarek Vasut2016-05-06-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kingston DT Ultimate USB 3.0 stick is sensitive to this first Get Descriptor request and if the request is not in a separate microframe, the stick refuses to operate. Add slight delay, which is enough for one microframe to pass on any USB spec revision. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: Wait after sending Set Configuration requestMarek Vasut2016-05-06-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices, like the SanDisk Cruzer Pop need some time to process the Set Configuration request, so wait a little until they are ready. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: Don't init pointer to zero, but NULLMarek Vasut2016-05-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pointer should always be inited to NULL, not zero (0). These are two different things and not necessarily equal. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: ehci-mx6: allow board_ehci_hcd_init to failStefan Agner2016-05-06-2/+5
| |/ | | | | | | | | | | | | | | | | | | | | There could be runtime determined board specific reason why a EHCI initialization fails (e.g. ENODEV if a Port is not available). In this case, properly return the error code. While at it, that function (board_ehci_hcd_init) has actually two documentation blocks... Use the correct function name for the documentation block of board_usb_phy_mode. Signed-off-by: Stefan Agner <stefan@agner.ch>
* | imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | test/py: dfu: wait for USB device to go away at bootStephen Warren2016-05-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | It can take a while for a host machine to notice that a USB device has disconnected, and process the change. At the end of the DFU test, we wait up to 10 seconds for this to happen. This change makes the test wait the same (up to) 10 seconds at the start of the test for any previously active USB device-mode session to be cleaned up. Such as session might have been used to download U-Boot into memory for example; this is certainly true on my Tegra test systems. This changes should solve the DFU test intermittency issues I've been seeing on some Tegra devices. Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-11-09 15:03:26 +0000