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* Merge branch 'for-tom' of git://git.denx.de/u-boot-dmTom Rini2014-09-26-110/+89
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| * spi: Add brackets and tidy defines in spi.hSimon Glass2014-09-26-12/+12
| | | | | | | | | | | | | | | | Some of the #defines in spi.h are not bracketed. To avoid future mistakes add brackets. Also add an explanatory comment for SPI_CONN_DUAL_... Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * dm: spi: Move cmd device code into its own functionSimon Glass2014-09-26-21/+32
| | | | | | | | | | | | | | | | In preparation for changing the error handling in this code for driver model, move it into its own function. Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: config: Enable all SPI flash chipsSimon Glass2014-09-26-1/+7
| | | | | | | | | | | | | | | | | | Sandbox may as well support everything. This increases the amount of code that is built/tested by sandbox, and also provides access to all the supported SPI flash devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sandbox: Convert SPI flash emulation to use sf_paramsSimon Glass2014-09-26-76/+38
| | | | | | | | | | | | | | | | | | | | | | At present sandbox has its own table of supported SPI flash chips. Now that the SPI flash system is fully consolidated and has its own list, sandbox should use that. This enables us to expand the number of chips that sandbox supports. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-251/+1018
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| * | board/ls1021aqds: Add DDR4 supportYork Sun2014-09-25-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
| * | driver/ddr/fsl: Fix DDR4 driverYork Sun2014-09-25-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Move u-boot location to make room for RCWYork Sun2014-09-25-1/+1
| | | | | | | | | | | | | | | | | | When booting with SP, RCW resides at the beginning of IFC NOR flash. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Enable secondary coresYork Sun2014-09-25-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-25-89/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | fdt_support: Make of_bus_default_count_cells non staticArnab Basu2014-09-25-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_bus_default_count_cells can be used to get the #address-cells and #size-cells defined by the current node's parent node. This is required when using of_read_number to read from FDT nodes that can be 32 or 64 bytes depending on values defined by the parent. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> CC: Scott Wood <scottwood@freescale.com>
| * | fdt_support: Move of_read_number to fdt_support.hArnab Basu2014-09-25-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is being done so that it can be used outside 'fdt_support.c'. Making life more convenient when reading device node properties that can be 32 or 64 bits long. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Cc: Scott Wood <scottwood@freescale.com>
| * | driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-25-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-25-5/+89
| | | | | | | | | | | | | | | | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-108/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
| * | board/ls2085a: Add support of NOR and NAND flash for simulatorPrabhakar Kushwaha2014-09-25-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of NOR and NAND flash for simulator target. Here IFC - CS0: NOR flash IFC - CS1: NAND flash Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha2014-09-25-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/ls2085a: Update env_addr after NOR flash relocationPrabhakar Kushwaha2014-09-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-39/+82
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| * | powerpc: add --bss-plt to LDFLAGSChris Packham2014-09-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected) it is necessary to specify --bss-plt to get the final blrl in the _GOT2_TABLE_. Without this the last symbol does not get it's address relocated. For the P2041RDB board this ended up being NetArpWaitTimerStart which caused the ARP packets to timeout immediately. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * | powerpc/t104xrdb: Set DDR ODT to 75ohmPriyanka Jain2014-09-24-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: Serdes protocol "00" is supportedEbony Zhu2014-09-24-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | "0x00" is a valid serdes protocol for QorIQ parts, and can not be used to test whether the serdes is enabled or disabled. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | B4860QDS: Enable mac command supportShaveta Leekha2014-09-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | One of the I2C EEPROM is used to store/save and edit mac addresses of ports. this patch add required CONFIG to support the same Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | powerpc/b4860: Updated default hwconfig to enable only cpc2Shaveta Leekha2014-09-24-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Though by editing hwconfig en_cpc option, CPC1 can also be enabled. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/8xxx: Fix in USB device-tree fixupramneek mehresh2014-09-24-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following issues in USB device-tree fixup: - returns when either dr_mode or phy_type not defined. This was terminating fix-up when only either property was defined in hwconfig string - updates dr_mode_type or dr_phy_type with junk value when their index is -1. Now these are updated only when their respective index is pointing to relevant types in modes[] and phys[] array - dr_mode_type and dr_phy_type were not NULL for each controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t104xrdb: Add T1042RDB board supportvijay rai2014-09-24-10/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB is a Freescale reference board that hosts the T1042 SoC (and variants). The board is similar to T1040RDB, T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). T1042RDB is configured with serdes protocol 0x86 which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 DTSEC1, DTSEC2 are not connected on board. This Patch - add T1042RDB support - updates README file for T1042RDB details and update commands for switching to alternate banks from vBank0 to vBank4 and vice versa This patch also does minor clean ups for fdt defines for T1042RDB and T1042RDB_PI board Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t104xrdb: Add Support of rcw for T1042RDB in u-bootvijay rai2014-09-24-4/+14
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch adds support of rcw for T1042RDB, it makes following changes : - Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB - Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates comments for valid serdes protocol which is 0x06 - Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | nand/denali: Document CONFIG symbolsScott Wood2014-09-25-0/+6
| | | | | | | | | | | | | | | | | | The patch "nand/denali: Adding Denali NAND driver support" introduced two config symbols without documenting them. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | nand/denali: Adding Denali NAND driver supportChin Liang See2014-09-25-0/+1673
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the Denali NAND driver support into U-Boot. This driver is leveraged from Linux with commit ID fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali controller 64 variance, you need to declare macro CONFIG_SYS_NAND_DENALI_64BIT. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mtd: nand: Fix length bug in ioread16_rep() and iowrite16_rep()Stefan Roese2014-09-25-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific and have been introduced with the Linux MTD v3.14 sync. While introducing these functions, the length for the loop has been miscalculated. The ">> 1" is already present in the caller. So lets remove it in the function. Tested on omap3_ha. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Heiko Schocher <hs@denx.de>
* | mtd: nand: am335x: Fix 'bit-flip' errors in SPLRostislav Lisovy2014-09-25-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html The issue was partially fixed with the cc81a5291910d7a.git however this has to be done to fix the SPL. The original author of the code is Belisko Marek <marek.belisko@gmail.com> Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
* | checkpatch: remove unnecessary + after {8,8}Joe Perches2014-09-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pick the following commit from Linux kernel: commit 66cb4ee0e52ca721f609fd5eec16187189ae5fda Author: Joe Perches <joe@perches.com> Date: Wed Sep 10 09:40:47 2014 +1000 checkpatch: remove unnecessary + after {8,8} There's a useless "+" use that needs to be removed as perl 5.20 emits a "Useless use of greediness modifier '+'" message each time it's hit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com>
* | kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfigMasahiro Yamada2014-09-25-81/+46
| | | | | | | | | | | | | | | | | | | | | | This option specifies the default Device Tree used for the run-time configuration of U-Boot. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Michal Simek <michal.simek@xilinx.com>
* | kconfig: move CONFIG_OF_* to KconfigMasahiro Yamada2014-09-25-61/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves: CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_OF_EMBED CONFIG_OF_HOSTFILE Because these options are currently not supported for SPL, the "Device Tree Control" menu does not appear in the SPL configuration. Note: zynq-common.h should be adjusted so as not to change the default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | tools: remove reformat.pyMasahiro Yamada2014-09-24-132/+0
| | | | | | | | | | | | | | This tools is unnecessary since commit f6c8f38ec601 (tools/genboardscfg.py: improve performance more with Kconfiglib). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | README.clang: update FreeBSD instructionsJeroen Hofstee2014-09-24-4/+4
| | | | | | | | | | | | | | | | | | | | The mentioned binutils port got removed while the patch was pending. As Ian pointed out there is another port providing the binutils for arm now. Update the instructions accordingly. Cc: ian@FreeBSD.org Cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | compiler_gcc: prevent redefining attributesJeroen Hofstee2014-09-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The libc headers on FreeBSD and likely related projects as well contain an header file, cdefs.h which provides similiar functionality as linux/compiler.h. It provides compiler independent defines like __weak __packed, to allow compiling with multiple compilers which might have a different syntax for such extension. Since that header file is included in multiple standard headers, like stddef.h and stdarg.h, multiple definitions of those defines will be present if both are included. When compiling u-boot the compiler will warn about it hundreds of times since e.g. common.h will include both files indirectly. commit 7ea50d52849fe8ffa5b5b74c979b60b1045d6fc9 "compiler_gcc: do not redefine __gnu_attributes" prevented such redefinitions, but this was undone by commit fb8ffd7cfc68b3dc44e182356a207d784cb30b34 "compiler*.h: sync include/linux/compiler*.h with Linux 3.16". Add the checks back where necessary to prevent such warnings. As the original patch this checkpatch warning is ignored: "WARNING: Adding new packed members is to be done with care" Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | kbuild: refactor some makefilesMasahiro Yamada2014-09-24-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Move driver/core/, driver/input/ and drivers/input/ entries from the top Makefile to drivers/Makefile [2] Remove the conditional by CONFIG_DM in drivers/core/Makefile because the whole drivers/core directory is already selected by CONFIG_DM in the upper level [3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile [4] Simplify common/Makefile - both CONFIG_DDR_SPD and CONFIG_SPD_EEPROM are boolean macros so they can directly select objects Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* | common.h: remove MIN, MAX, MIN3, MAX3 macrosMasahiro Yamada2014-09-24-6/+0
| | | | | | | | | | | | | | Now MIN, MAX, MIN3, MAX are not used. Going forward, use min, max, min3, max3. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-39/+39
| | | | | | | | | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | compiler.h: remove duplicated uninitialized_varJeroen Hofstee2014-09-24-3/+0
| | | | | | | | | | | | | | | | | | | | | | Since clang has a different definition for uninitialized_var it will complain that it is redefined in include/compiler.h. Since these are already defined in linux/compiler.h just remove this instance. Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | cmd_nand: Update (nand_info_t*)nand after arg_off(_size) callRostislav Lisovy2014-09-24-2/+4
| | | | | | | | | | | | | | | | | | | | The arg_off() and arg_off_size() update the 'current NAND device' variable (dev). This is then used when assigning the (nand_info_t*)nand value. Place the assignment after the arg_off(_size) calls to prevent using incorrect (nand_info_t*) nand value. Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
* | linker_lists: fix commentMasahiro Yamada2014-09-24-2/+2
| | | | | | | | | | | | | | | | The section name and the C variable name seem to be opposite. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* | kconfig: remove config_cmd_defaults.hMasahiro Yamada2014-09-24-14/+0
| | | | | | | | | | | | | | Now config_cmd_defaults.h is empty so it can be deleted safely. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: move CONFIG_CMD_IMPORTENV to KconfigMasahiro Yamada2014-09-24-3/+7
| | | | | | | | | | | | | | | | | | | | Since CONFIG_CMD_IMPORTENV is defined in config_cmd_defaults.h, it should be enabled for all the boards except bf506f-ezkit that undefs it explicitely. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | kconfig: move CONFIG_CMD_GO to KconfigMasahiro Yamada2014-09-24-1/+6
| | | | | | | | | | | | | | | | | | | | Since CONFIG_CMD_GO is defined in config_cmd_defaults.h (and no board undefs it its own header), it can be moved to Kconfig with the default value "y". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | kconfig: move CONFIG_CMD_EXPORTENV to KconfigMasahiro Yamada2014-09-24-2/+7
| | | | | | | | | | | | | | | | | | | | Since CONFIG_CMD_EXPORTENV is defined in config_cmd_defaults.h, it should be enabled for all the boards except bf506f-ezkit that undefs it explicitely. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | kconfig: move CONFIG_CMD_CRC32 to KconfigMasahiro Yamada2014-09-24-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since CONFIG_CMD_CRC32 is defined in config_cmd_defaults.h, it is enabled for all the boards except the ones undefining it explicitly: kwb tseries_mmc tseries_nand tseries_spi vct_platinum_onenand_small vct_platinum_small vct_platinumavc_onenand_small vct_platinumavc_small vct_premium_onenand_small vct_premium_small The default value of this config option should be "y" and "# CONFIG_CMD_CRC32 is not set" should be added for those exceptions. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
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