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* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-10-20-74/+2558
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| * ls102x: Add support for secure boot and enable blob commandRuchika Gupta2014-10-16-0/+16
| | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-16-0/+29
| | | | | | | | | | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: Add command for encapsulating/decapsulating blobsRuchika Gupta2014-10-16-2/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure bootRuchika Gupta2014-10-16-1/+9
| | | | | | | | | | | | | | | | | | | | | | By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta2014-10-16-0/+39
| | | | | | | | | | | | | | | | | | Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-16-0/+91
| | | | | | | | | | | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+1834
| | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec : Change accessor function to take care of endiannessRuchika Gupta2014-10-16-6/+29
| | | | | | | | | | | | | | | | | | | | | | SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec : Move SEC CCSR definition to common includeRuchika Gupta2014-10-16-66/+89
| | | | | | | | | | | | | | | | | | Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/P1010RDB:Update RESET_VECTOR_ADDRESS for 768KB u-boot sizeRuchika Gupta2014-10-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_RESET_VECTOR_ADDRESS to reflect the same for P1010 SPI Flash Secure boot target. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Modified subject to P1010RDB] Reviewed-by: York Sun <yorksun@freescale.com>
* | video: ipu_disp: remove pixclk fixupJeroen Hofstee2014-10-16-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ipu display insists on having a lower_margin smaller then 2. If this is not the case it will attempt to force it and adjust the pixclk accordingly. This multiplies pixclk in Hz with the width and height, since this is typically a * 10^7 * b * 10^2 * c * 10^2 this will overflow the uint_32 and make things even worse. Since this is a bootloader and the adjustment is neglectible, just force it to two and warn about it. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | video: ipu: fix debug and commentJeroen Hofstee2014-10-16-5/+4
| | | | | | | | | | | | | | | | - fix debug pixel clk display and add unit - fix some comments Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | lcd: Fix build error with CONFIG_LCD_BMP_RLE8Simon Glass2014-10-16-2/+3
|/ | | | | | | | Add a block to avoid a build error with the variable declaration. Enable the option on sandbox to prevent an error being introduced in future. Signed-off-by: Simon Glass <sjg@chromium.org>
* Prepare v2014.10Tom Rini2014-10-14-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* sunxi: axp152: dcdc3 scale is 50mV / step not 25mV / stepHans de Goede2014-10-13-1/+1
| | | | | | | | | | Currently uboot wrongly uses 25mV / step for dcdc3, this is a copy and paste error introduced when adding the axp152_mvolt_to_target during review of the axp152.c driver. This results in u-boot setting Vddr to 2.3V instead of 1.5V. This commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Makefile: drop "tools-only" from no-dot-config-targetsTom Rini2014-10-13-1/+1
| | | | | | | | | With the introduction of CONFIG_LOCALVERSION support we cannot build tools without having a config file (as we won't know our PLAIN_VERSION until then). Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-10-10-1003/+5360
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| * Merge branch 'u-boot-socfpga/topic/arm/socfpga-20141010' into ↵Albert ARIBAUD2014-10-11-1/+8
| |\ | | | | | | | | | 'u-boot-arm/master'
| | * arm: socfpga: Use EMAC1 on SoCDKMarek Vasut2014-10-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoCDK uses EMAC1, not EMAC0. This patch fixes the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
| | * arm: socfpga: add MAINTAINERS entryPavel Machek2014-10-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MAINTAINERS entry. Signed-off-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-12267/+2816
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| * | arm, at91: add generic board support for the taurus and corvus boardHeiko Schocher2014-10-10-0/+4
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: switch at91sam9263ek to generic boardBo Shen2014-10-10-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | sama5d3xek: run PHY's configAndreas Bießmann2014-10-10-9/+20
| | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com>
| * | macb: simplify gmac initialisationAndreas Bießmann2014-10-10-17/+8
| | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Bo Shen <voice.shen@atmel.com>
| * | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-10-557/+840
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| | * | odroid: clock: set aclk_cores to 200MHzPrzemyslaw Marczak2014-10-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change fixes suspend/resume issue in the kernel caused by the wrong 'aclk_cores' clock value expected by the kernel. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: update maintainer of Snow and SMDK5420 boardMasahiro Yamada2014-10-08-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The email address of Rajeshwari Shinde <rajeshwari.s@samsung.com> is not working. This commit gives Akshay the maintainership of Snow and SMDK5420 boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | armv7: s5pc1xx: improve cache handlingRobert Baldyga2014-10-08-30/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move cache handling code to C file, and add enable_caches() and disable_caches() functions. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: Enable pre-relocation malloc()Simon Glass2014-10-08-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable this feature to support driver model before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | samsung: Enable device tree for smdkc100Simon Glass2014-10-08-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change this board to add a device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | samsung: Enable device tree for s5p_goniSimon Glass2014-10-08-7/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | config: Move smdkv310 to use common exynos4 fileSimon Glass2014-10-08-51/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | config: Move arndale to use common exynos5250 fileSimon Glass2014-10-08-212/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the arndale features are common with other exynos5250 boards. To permit easier addition of driver model support, use the common file. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: config: Move cros_ec and tps65090 out of smdk boardsSimon Glass2014-10-08-18/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so move the settings into a separate common file to be used by those that need it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: Move common smdk5420 things to common fileSimon Glass2014-10-08-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few things are common but are not in the common file. Fix this and rename the file to fit with the other exynos*-common files. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: Move common exynos settings into a common fileSimon Glass2014-10-08-171/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since exynos4 and exyno5 share many settings, we should move these into a common file to avoid duplication. In effect the changes are that all exynos boards now have EXT4 and FAT write support. This affects exynos5250 and exynos5420 which previously did not. This also disables the ext2 commands which are equivalent to ext4 anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: Rename -dt config files to -commonSimon Glass2014-10-08-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want exynos5250-dt.h to be a board which can support any exynos5250 device. This matches the naming used by Linux. As a first step, rename the existing -dt files to -common to make it clear they are common files, and not specific boards. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: dts: Add device tree node for cros_ec keyboardSimon Glass2014-10-08-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a keyboard definition so that the keyboard can be used on pit. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | dm: exynos: Split out the cros_ec driversSimon Glass2014-10-08-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the driver model conversion we are going to be using driver model for SPI and not for I2C. This works OK so long as a board doesn't need both dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow uses I2C we need to split the configs so that only one driver is compiled for each platform. We can fix this later when driver model supports I2C. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | cros_ec: exynos: Use the correct tps65090 driver in each caseSimon Glass2014-10-08-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards cannot due to a hardware design decision. Select the correct driver to use in each case. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | cros_ec: power: Add a tunnelled version of the tps65090 driverSimon Glass2014-10-08-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus. When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos5: Enable data cacheSimon Glass2014-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Things run faster when the data cache is enabled, so turn it on along with the 'dcache' command. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos: Use 900MHz ARM frequency in SPL for peach_pitSimon Glass2014-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Merge branch 'uboot'Minkyu Kang2014-10-07-2031/+11739
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| | * \ \ Merge branch 'master' of http://git.denx.de/u-boot-samsungMinkyu Kang2014-10-07-30/+30
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| | | * | | Revert "odroid: set MPLL clock to 880MHz"Minkyu Kang2014-09-11-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b09200639d4c052e2bdf0df6fe843b7a8bcf01cc.
| * | | | | compulab: eeprom: add default eeprom busNikita Kiryanov2014-10-09-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add default eeprom bus setting. This addresses the trimslice compile error that was introduced with the addition of this setting. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | | | | arm: rmobile: r8a7794: Skip initialize L2 cacheNobuhiro Iwamatsu2014-10-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of rmobile SoCs. The initialize L2 cache in lowlevel_init_ca15.S only needed for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15. This adds Skip to initialize L2 cache when r8a7794. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
generated by cgit v1.1 at 2024-09-19 21:00:22 +0000