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* omap4_panda: Disable ext2/3/4 support in SPLTom Rini2016-09-21-0/+1
| | | | | | | Pandaboard is growing again, disable EXT2/3/4 support in SPL save more space. Signed-off-by: Tom Rini <trini@konsulko.com>
* clk.h: Add <asm/errno.h>Tom Rini2016-09-21-0/+1
| | | | | | | Since we return -ENOSYS in some cases we must have <asm/errno.> available. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-09-21-180/+2115
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| * MIPS: Hang if run on a secondary CPUPaul Burton2016-09-21-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Fix cache maintenance in relocate_code & simplifyPaul Burton2016-09-21-26/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The relocate_code function was handling cache maintenance incorrectly. It copied U-Boot to its new location, flushed the caches & then proceeded to apply relocations & jump to the new code without flushing the caches again. This is problematic as the instruction cache could potentially have already fetched instructions that hadn't had relocs applied. Rework this to perform the flush_cache call using the code in the original copy of U-Boot, after having applied relocations to the new copy of U-Boot. The new U-Boot can then be jumped to safely once that cache flush has been performed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * boston: Introduce support for the MIPS Boston development boardPaul Burton2016-09-21-0/+740
| | | | | | | | | | | | | | | | | | | | This patch introduces support for building U-Boot to run on the MIPS Boston development board. This is a board built around an FPGA & an Intel EG20T Platform Controller Hub, used largely as part of the development of new CPUs and their software support. It is essentially the successor to the older MIPS Malta board. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * clk: boston: Providea simple driver for Boston board clocksPaul Burton2016-09-21-0/+119
| | | | | | | | | | | | | | | | | | | | Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: syscon: Provide a generic syscon driverPaul Burton2016-09-21-0/+11
| | | | | | | | | | | | | | | | Provide a trivial syscon driver matching the generic "syscon" compatible string, allowing for simple system controllers to be used without a custom driver just as in Linux. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * dm: core: Match compatible strings in order of priorityPaul Burton2016-09-21-37/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device model drivers have previously been matched to FDT nodes by virtue of being the first driver in the driver list to be compatible with the node. This ignores the fact that compatible strings in the device tree are listed in order of priority - that is, if we have a node with 2 compatible strings & a driver that matches each then we should always probe the driver that matches the first compatible string. Fix this by looping through the compatible strings for a node when attempting to bind it in lists_bind_fdt and checking each driver for a match of the first string, then each driver for a match of the second string etc. Effectively this inverts the loops over compatible strings & drivers. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * dm: regmap: Implement simple regmap_read & regmap_writePaul Burton2016-09-21-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | The regmap_read & regmap_write functions were previously declared in regmap.h but not implemented anywhere. The regmap implementation & commit message of 6f98b7504f70 ("dm: Add support for register maps (regmap)") indicate that only memory mapped accesses are supported for now, so providing simple implementations of regmap_read & regmap_write is trivial. The access size is presumed to be 4 bytes & endianness is presumed native, which are the defaults for the regmap code in Linux. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * net: pch_gbe: Make 64 bit safePaul Burton2016-09-21-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The pch_gbe driver previously casted pointers to & from unsigned 32 bit integers in many locations. This breaks the driver on 64 bit systems, producing streams of compiler warnings about mismatched pointer & integer sizes and then failing to keep track of addresses correctly at runtime. Fix the driver for 64 bit systems by using unsigned longs in place of the previously used 32 bit integers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: pch_gbe: Use dm_pci_map_bar to discover MMIO basePaul Burton2016-09-21-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Reading the PCI BAR & converting the result to a physical address is not safe across all architectures. For example on MIPS the virtual:physical mapping is not 1:1, so we cannot directly make use of the physical address. Use the more generic BAR-mapping function dm_pci_map_bar to discover the MMIO base address, which should work across architectures. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * pci: Flip condition for detecting non-PCI parent devicesPaul Burton2016-09-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In pci_uclass_pre_probe an attempt is made to detect whether the parent of a device is a PCI device and that the device is thus a bridge. This was being done by checking whether the parent of the device is of the UCLASS_ROOT class. This causes problems if the PCI controller is a child of some other non-PCI node, for example a simple-bus node. For example, if the device tree contains something like the following then pci_uclass_pre_probe would incorrectly believe that the PCI controller is a bridge, with a PCI parent: / { some_child { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <>; pci_controller: pci@10000000 { compatible = "my-pci-controller"; device_type = "pci"; reg = <0x10000000 0x2000000>; }; }; }; Avoid this incorrect detection of bridges by instead checking whether the parent devices class is UCLASS_PCI and treating a device as a bridge when this is true, making use of device_is_on_pci_bus to perform this test. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: xilinx: Add a driver for Xilinx AXI to PCIe bridgePaul Burton2016-09-21-0/+228
| | | | | | | | | | | | | | | | | | | | This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is mostly a case of implementing PCIe ECAM specification, but with some quirks about what devices are valid to access. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dt-bindings: Add interrupt-controller/mips-gic.h headerPaul Burton2016-09-21-0/+9
| | | | | | | | | | | | | | | | Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header from Linux, such that we can use device trees which include it without modification. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * serial: ns16550: Support clocks via phandlePaul Burton2016-09-21-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: Use dummy clk_get_by_* functions when CONFIG_CLK is disabledPaul Burton2016-09-21-1/+1
| | | | | | | | | | | | | | | | | | The implementations of clk_get_by_index & clk_get_by_name are only available when CONFIG_CLK is enabled. Provide the dummies when this is not the case in order to avoid build failures. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * MIPS: Ensure cache ops complete in mips_cache_resetPaul Burton2016-09-21-0/+2
| | | | | | | | | | | | | | | | | | | | Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Clear hazard between TagLo writes & cache opsPaul Burton2016-09-21-0/+1
| | | | | | | | | | | | | | | | | | Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Ensure Config.K0=2 applies before any memory accessesPaul Burton2016-09-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Malta: Enable CM & L2 supportPaul Burton2016-09-21-6/+2
| | | | | | | | | | | | | | | | | | Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Join the coherent domain when a CM is presentPaul Burton2016-09-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we will need to do so if we wish to make use of IOCUs to have cache-coherent DMA in U-Boot (and on some systems there is no choice in that matter). When a CM is present, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: L2 cache supportPaul Burton2016-09-21-6/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Map CM Global Control RegistersPaul Burton2016-09-21-0/+88
| | | | | | | | | | | | | | Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Define register names for cache initPaul Burton2016-09-21-19/+23
| | | | | | | | | | | | | | | | Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing register assignments more easily. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: If we don't need DDR for cache init, init cache firstPaul Burton2016-09-21-0/+9
| | | | | | | | | | | | | | | | | | | | On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Preserve Config implementation-defined bitsPaul Burton2016-09-21-2/+4
| | | | | | | | | | | | | | | | | | | | The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Enable use of the instruction cache earlierPaul Burton2016-09-21-8/+13
| | | | | | | | | | | | | | | | | | Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Probe cache line sizes once during bootPaul Burton2016-09-21-18/+45
| | | | | | | | | | | | | | | | | | | | | | Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: ath79: Use mach_cpu_init instead of arch_cpu_initPaul Burton2016-09-21-1/+1
| | | | | | | | | | | | | | | | In order to prepare for MIPS arch code making use of arch_cpu_init in a later patch, stop using it from ath79 SoC code & instead use the new mach_cpu_init which is provided for this purpose. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * board_f: Add a mach_cpu_init callbackPaul Burton2016-09-21-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we have a mismash of architectures which use arch_cpu_init from architecture-wide code (arc, avr32, blackfin, mips, nios2, xtensa) and architectures which use arch_cpu_init from machine/SoC level code (arm, x86). In order to clean this mess up & allow for both use cases, introduce a new mach_cpu_init callback which is run immediately after arch_cpu_init. This will allow for architectures to have arch-wide code without needing individual machines to all implement their own arch_cpu_init with a call to some common function. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mips: Add MIPSfpga platform supportZubair Lutfullah Kakakhel2016-09-21-0/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPSfpga is an FPGA based dev platform. In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks The FPGA dev board used is the Nexys4DDR board by Digilent. For more information, check the Readme file in board/imgtec/xilfpga Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: xilfpga: Add device tree filesZubair Lutfullah Kakakhel2016-09-21-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | Mostly the same as the Kernel upstream device tree file except for - alias for the serial console node - ethernet node as the ethernet stuff isn't upstream on kernel.org yet - uart clock-frequency passed directly in the node Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * net: emaclite: Enable driver for MIPSZubair Lutfullah Kakakhel2016-09-21-1/+1
| | | | | | | | | | | | Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: emaclite: use __raw_readl/writel instead of weird defineZubair Lutfullah Kakakhel2016-09-21-41/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | out_be32 and in_be32 are actually #defined to little endian writel/readl in arch/microblaze. Just use __raw_writel/readl instead. That is also what is used in the Linux kernel driver for this IP block Tested on MIPSfpga. Can tftp a kernel. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: emaclite: Use ioremap_nocacheZubair Lutfullah Kakakhel2016-09-21-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Virtual to physical mapping isn't necessarily 1:1 for all architectures Using ioremap_nocache allows for the arch code to translate the physical address to a virtual address. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-mmcTom Rini2016-09-21-52/+164
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| * | mmc: dw_mmc: push/pop all FIFO data if any data requestJacob Chen2016-09-21-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DTO interrupt occurred, there are any remaining data still in FIFO due to RX FIFO threshold is larger than remaining data. It also causes that dwmmc didn't trigger RXDR interrupt, so is TX. It's responsibility of driver to read remaining bytes on seeing DTO interrupt. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * | mmc: sdhci: Add the programmable clock mode supportWenyou Yang2016-09-20-10/+42
| | | | | | | | | | | | | | | | | | Add the programmable clock mode for the clock generator. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | mmc: sd: optimize erasePeng Fan2016-09-20-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To SD, there is no erase group, then the value erase_grp_size will be default 1. When erasing SD blocks, the blocks will be erased one by one, which is time consuming. We use AU_SIZE as a group to speed up the erasing. Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB. `time mmc erase 0x100000 0x2000` time: 44.856 seconds (before optimization) time: 0.335 seconds (after optimization) Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com>
| * | mmc: sd: extracting erase related information from sd statusPeng Fan2016-09-20-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to read SD_STATUS information. According to the information, get erase_timeout/erase_size/erase_offset. Add a structure sd_ssr to include the erase related information. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com>
| * | mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_MAX_TIMEOUTMasahiro Yamada2016-09-20-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | No need for per-SoC adjustment for this parameter. It should be determined by the slowest hardware. Currently, no board overrides this CONFIG, so 3.2 sec is large enough. (If not, we can make it even larger.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_DEFAULT_TIMEMasahiro Yamada2016-09-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This CONFIG is not configurable since it is not guarded by #ifndef. Nobody has complained about that, so there is no need to keep it as a CONFIG option. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: sdhci: move SDMA capability check to sdhci_setup_cfg()Masahiro Yamada2016-09-20-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_BLK is enabled, add_sdhci() is never called. Move this quirk handling to sdhci_setup_cfg(), which is now the central place for hardware capability checks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: sdhci: move broken voltage quirk handling to sdhci_setup_cfg()Masahiro Yamada2016-09-20-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_BLK is enabled, add_sdhci() is never called. Move this quirk handling to sdhci_setup_cfg(), which is now the central place for hardware capability checks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: sdhci: move error message to more relevant placeMasahiro Yamada2016-09-20-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | "Hardware doesn't specify base clock frequency" may not be only the error case of sdhci_setup_cfg(). It is better to print this where the corresponding error is triggered. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: sdhci: move sdhci_reset() call to sdhci_init()Masahiro Yamada2016-09-20-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | If CONFIG_BLK is enabled, add_sdhci() is never called. So, sdhci_reset() is not called, either. This is a problem for my board as it needs the reset to start from a sane state. Move the add_sdhci() call to sdhci_init(), which is visited by both of the with/without CONFIG_BLK cases. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-09-20-243/+882
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| * | dtoc: Add methods for reading data from propertiesSimon Glass2016-09-18-0/+25
| | | | | | | | | | | | | | | | | | | | | Provide easy helpers for reading integer, string and boolean values from device-tree properties. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dtoc: Correct quotes in fdt_utilSimon Glass2016-09-18-1/+1
| | | | | | | | | | | | | | | | | | | | | The style is to use single quotes for strings where possible. Adjust this function. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-01 15:53:53 +0000