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| * | Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-11-03-32/+3421
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| | * | am335x: add initial AM335x IDK board supportMatthias Fuchs2012-11-02-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the am335x_evm board for the AM335x IDK. The IDK board uses MII for the ethernet phy (same as Beaglebone board) and MMC0 for storage (but without card detect line). The IDK uses UART3 for console. So u-boot must be build with CONFIG_SERIAL4 and CONFIG_CONS_INDEX=4 or for the am335x_evm_uart3 board configuration as introduced by Andrew Bradfords recent patch series "am33xx: Enable UART {1,2,3,4,5}...". When using the IDK with console on UART0, those patches are not required. In this case the board slightly needs to be modified. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| | * | omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFFTom Rini2012-10-30-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini <trini@ti.com>
| | * | am335x: add mux config for DDR3 version of beagleboneKoen Kooi2012-10-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following boothang in SPL: Unknown board, cannot configure pinmux.### ERROR ### Please RESET the board ### Future commits will add pinmuxes for more on-board peripherals. Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
| | * | eco5pk: Add new board and default configRaphael Assenat2012-10-30-0/+594
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Raphael Assenat <raph@8d.com> [trini: Squash boards.cfg / MAINTAINERS change into main patch] Signed-off-by: Tom Rini <trini@ti.com>
| | * | New board support: Nokia RX-51 aka N900Pali Rohár2012-10-30-0/+2193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on previous work by: Alistair Buxton <a.j.buxton@gmail.com> Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Cc: Ивайло Димитров <freemangordon@abv.bg>
| | * | cfb_console: Add support for some ANSI terminal escape codesPali Rohár2012-10-30-9/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add optional support for some ANSI escape sequences to the cfb_console driver. Define CONFIG_CFB_CONSOLE_ANSI to enable cursor moving, color reverting and clearing the cfb console via ANSI escape codes. Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| | * | Add power bus message definitions in twl4030.hPali Rohár2012-10-30-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Code copied from linux kernel 3.0.0 from file include/linux/i2c/twl.h * commit 6523b148b44be38d89c2ee9865d34da30d9f5f1c Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
| | * | arm bootm: Allow to pass board specified atagsPali Rohár2012-10-30-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Board can implement function setup_board_tags which is used for adding atags Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
| | * | am335x_evm: Enable use of UART{1,2,3,4,5}Andrew Bradford2012-10-25-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add targets of am335x_evm_uart{1,2,3,4,5} to have serial input/output on UART{1,2,3,4,5} for use with the Beaglebone RS232 cape, am335x_evm daughterboard, and other custom configurations. Modify target for am335x_evm to include SERIAL1 and CONS_INDEX=1 options in order to clarify UART selection requirements. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | * | serial: ns16550: Enable COM5 and COM6Andrew Bradford2012-10-25-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | Increase the possible number of ns16550 serial devices from 4 to 6. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | * | am33xx: Enable UART{1,2,3,4,5} pin-muxAndrew Bradford2012-10-25-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or on the am335x_evm daughterboard, enable the proper pin-muxing. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | * | am33xx: Enable UART{1,2,3,4,5} clocksAndrew Bradford2012-10-25-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| * | | arm720t: add back common.h includeAllen Martin2012-10-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add back common.h header that was removed in previous patch so that CONFIG_TEGRA can be evaluated correctly. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | serial: remove calls to serial_assign()Allen Martin2012-10-29-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove calls to serial_assign() that are failing now that it returns a proper error code. This calls were not actually doing anything because they passed the name of a stdio_dev when a serial_device name is exptectd. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: combine duplicate Makefile rulesStephen Warren2012-10-29-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rules to generate u-boot-{no,}dtb-tegra.bin were almost identical. Combine them into a single paremeterized rule. This will allow the next patch to edit a single rule, rather than being cut/paste twice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra20: initialize variable to avoid compiler warningAllen Martin2012-10-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize this variable to avoid a compiler warning about possible use of uninitialized variable with gcc 4.4.6. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: move to common SPL frameworkAllen Martin2012-10-29-77/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change tegra SPL to use common SPL framework. Any tegra specific initialization is now done in spl_board_init() instead of board_init_f()/board_init_r(). Only one SPL boot target is supported on tegra, which is boot to RAM image. jump_to_image_no_args() must be overridden on tegra so the host CPU can be initialized. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | SPL: make jump_to_image_no_args a weak symbolAllen Martin2012-10-29-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change jump_to_image_no_args() to a weak symbol to allow override by SoC specific code. This is required by tegra because the SPL runs on a different CPU from the image it is loading, so tegra specific initialization is required to start the host CPU. Pass in spl_image as a parameter for the same reason. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: don't request GPIO from Seaboard's SPLStephen Warren2012-10-29-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seaboard has a GPIO that switches an external mux between Tegra's debug UART and SPI flash. This is initialized from the SPL so that SPL debug output can be seen. Simplify the code that does this, and don't actually request the GPIO in the SPL; just program it. This saves ~4.5K from the size of the SPL, mostly BSS due to the large gpio_names[] table that is no longer required. This makes Seaboard's SPL fit within the current max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: select between Seaboard/Ventana at compile timeStephen Warren2012-10-29-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seaboard and Ventana are very similar boards, and so share the seaboard.c board file. The one difference needed so far is detected at run-time by calling machine_is_ventana(). This bloats the Ventana build with code that is never used. Switch to detecting Ventana at compile time to remove bloat. This shaves ~5K off the SPL size on Ventana, and makes the SPL fit within the max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: derive CONFIG_SPL_MAX_SIZE instead of hard-coding itStephen Warren2012-10-29-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Tegra, the SPL and main U-Boot are concatenated together to form a single memory image. Hence, the maximum SPL size is the different in TEXT_BASE for SPL and main U-Boot. Instead of manually calculating SPL_MAX_SIZE based on those two TEXT_BASE, which can lead to errors if one TEXT_BASE is changed without updating SPL_MAX_SIZE, simply perform the calculation automatically. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: enhance u-boot.lds to detect over-sized SPLStephen Warren2012-10-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an ASSERT() to u-boot.lds to detect an SPL that doesn't fit within SPL_TEXT_BASE..SPL_MAX_SIZE. Different .lds files implement this check in two possible ways: 1) An ASSERT() like this 2) Defining a MEMORY region of size SPL_MAX_SIZE, and re-directing all linker output into that region. Since u-boot.lds is used for both SPL and main U-Boot, this would entail only sometimes defining a MEMORY region, and only sometimes performing that redirection, and hence option (1) was deemed much simpler, and hence implemented. Note that this causes build failures at least for NVIDIA Tegra Seaboard and Ventana. However, these are legitimate; the SPL doesn't fit within the required space, and this does cause runtime issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: nand: make ONFI detection workLucas Stach2012-10-29-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing bits to the Tegra NAND driver to make ONFI detection work properly. Also add it to the Tegra default config, as it seems to be a reasonable thing to have it available on all boards that use any kind of NAND. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: Whistler: remove unused USB aliasStephen Warren2012-10-29-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port USB1 on Whistler is intended as a device port for USB recovery. Whistler's DT currently contains an alias for this USB port, even though Whistler's config doesn't enable multiple USB controllers, so the alias is unused. Remove the unused alias for consistency for now. Similar, explicitly disable the port in the device tree too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: Seaboard: enable multiple USB portsStephen Warren2012-10-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree already contains the required configuration for both the USB1 and USB3 ports. Enable the required configuration options to enable both these ports, which in turn allows the USB1 port to be used. Note that on a true Seaboard, this port is typically used as a device port hosting Tegra's USB recovery protocol. However, on the Springbank derivative, this port is the only external USB port, so we enable it as a host port so that USB peripherals may be used. Enabling this port in U-Boot as a host port doesn't prevent the port from reverting to a device port when the CPU is reset into recovery mode. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: Harmony: enable ULPI USB portStephen Warren2012-10-29-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ULPI port is routed onto pins on the mini PCI Express connector. A standard breakout board may be used to access the port. * Add required DT entries to configure the ULPI port. * Setup up the ULPI pinmux in the board code. * Enable multiple USB controller and ULPI support in the board config. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: use standard variables to define load addressesStephen Warren2012-10-29-3/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, Tegra's default environment uses non-standard variables to define where boot scripts should load the kernel, FDT, and initrd. This change both changes the variable names to match those described in U-Boot's README, and shuffles their values around a little so that the values make a little more sense; see comments in the patch for rationale behind the values chosen. Note that this patch does remove the old non-standard variable "fdt_load" from the default environment, so this patch requires people to change their boot scripts. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: define CONFIG_SYS_BOOTMAPSZStephen Warren2012-10-29-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define indicates the size of the memory region where it is safe to place data passed to the Linux kernel (ATAGs, DTB, initrd). The value needs to be: a) Less than or equal to RAM size. b) Small enough that the area is not within the kernel's highmem region, since the kernel cannot access ATAGs/DTB/initrd from highmem. c) Large enough to hold the kernel+DTB+initrd. 256M seems large enough for (c) in most circumstances, and small enough to satisfy (a) and (b) across any possible Tegra board. Note that the user can override this value via environment variable "bootm_mapsize" if needed. The advantage of defining BOOTMAPSZ is that we no longer need to define variable fdt_high in the default environment. Previously, we defined this to prevent the DTB from being relocated to the very end of RAM, which on most Tegra systems is within highmem, and hence which would cause boot failures. A user can still define this variable themselves if they want the FDT to be either left in-place wherever loaded, or copied to some other specific location. Similarly, there should no longer be a strict requirement for the user to define initrd_high if using an initrd. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: add Colibri T20 board supportLucas Stach2012-10-29-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds board support for the Toradex Colibri T20 module. Working functions: - SD card boot - USB boot - Network - NAND environment Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: move common features to a common makefileMarc Dietrich2012-10-29-13/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Non-Nvidia boards to include newly added features (like emc clock scaling) it would be necessary to add each feature to their own board Makefile. This is because currently the top Makefile automaticly includes these features only for Nvidia boards. This patch adds a simple Makefile include so all new features become available for non-Nvidia board vendors. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-10-27-481/+1853
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| | * | | MX5: fix warning in clock.cStefano Babic2012-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch fix warnings compiling with ELDK-4.2: clock.c: In function 'get_standard_pll_sel_clk': clock.c:341: warning: 'freq' may be used uninitialized in this function Reported-by : Marek Vasut <marex@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | | imximage: make set_imx_hdr_v1/v2 easier to readTroy Kisky2012-10-20-19/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * | | imximage: change parameters to set_imx_hdrTroy Kisky2012-10-20-15/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call with the value the function will use instead of going through a pointer. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * | | imximage: delay setting of image sizeTroy Kisky2012-10-20-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When later we change to variable length header, we won't know the file size when set_imx_hdr is called. So this is prep work. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * | | imximage: fix size of image to load.Troy Kisky2012-10-20-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sbuf->st_size already includes sizeof(struct imx_header), so remove extra addition. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * | | imximage: move flash_offset check to common locationTroy Kisky2012-10-20-14/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the same check. Move check to before the set_imx_hdr call. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | | imximage: remove redundant setting of app_dest_ptrTroy Kisky2012-10-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | | imximage: check dcd_len as entries addedTroy Kisky2012-10-20-15/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the len was checked after the entire file was processed, so it could have already overflowed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * | | mx6qarm2: Enable DCACHE and CONFIG_MMC_BOUNCE_BUFFERFabio Estevam2012-10-20-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Data cache and CONFIG_MMC_BOUNCE_BUFFER can be safely enabled now. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mx6qsabre_common: Enable DCACHE and CONFIG_MMC_BOUNCE_BUFFERFabio Estevam2012-10-20-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Data cache and CONFIG_MMC_BOUNCE_BUFFER can be safely enabled now. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mx25pdk: Use internal RAM for stack pointerFabio Estevam2012-10-20-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use internal RAM for stack pointer as it is done in other i.MX boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mx5: Add workaround for ARM erratum ID 468414Fabio Estevam2012-10-17-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the software workaround for ARM erratum ID 468414. According to mx53/mx51 errata document: "ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request Description: Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request. The conditions are as follows: • Neon loads and stores must be in use • Neon L1 caching must be disabled • Trustzone must be configured and in use • The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations The issue is reported by ARM, erratum ID 468414, Category 2" Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mx6qsabrelite: enable DCache and MMC bounce bufferDirk Behme2012-10-17-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent U-Boot version 2012.07 has improved drivers (e.g. MMC and network/FEC) regarding DCache handling. So it should be safe to use the DCache on the i.MX6, now. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | | configs: mx53evk: Remove CONFIG_HAS_ETH1Fabio Estevam2012-10-17-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx53evk has only one Ethernet port, so remove CONFIG_HAS_ETH1 option. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | configs: mx51evk: Remove CONFIG_HAS_ETH1Fabio Estevam2012-10-17-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx51evk has only one Ethernet port, so remove CONFIG_HAS_ETH1 option. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | configs: mx53loco: Remove CONFIG_HAS_ETH1Fabio Estevam2012-10-17-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx53loco has only one Ethernet port, so remove CONFIG_HAS_ETH1 option. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mx53loco: Adapt the IPU clockFabio Estevam2012-10-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since PLL2 now has changed, it is necessary to adapt the CONFIG_IPUV3_CLK accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mx5: lowlevel_init.S: Fix PLL settings for mx53Fabio Estevam2012-10-17-33/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-12-29 09:34:00 +0000