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* x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-24-55/+12
| | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Bring up northbridge, pch and lpc after the CPUsSimon Glass2016-01-24-2/+18
| | | | | | | | | | These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't show an error when the MRC cache is up to dateSimon Glass2016-01-24-1/+5
| | | | | | | | | | When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour. Avoiding printing an error when this happens. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make x86_init_cpus() staticSimon Glass2016-01-24-3/+1
| | | | | | | | There are no other implementations of this function, and boards that need it can implement a CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move early init code into northbridge.cSimon Glass2016-01-24-82/+67
| | | | | | | | This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the dead MTRR codeSimon Glass2016-01-24-10/+0
| | | | | | | This is not used and MTRRs are set up elsewhere now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the thermal target correctlySimon Glass2016-01-24-11/+10
| | | | | | | | | This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move CPU init code into the driverSimon Glass2016-01-24-22/+4
| | | | | | | | Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use common CPU init codeSimon Glass2016-01-24-52/+79
| | | | | | | | | The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass2016-01-24-4/+3
| | | | | | | This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move sandybridge init to the lpc probe() methodSimon Glass2016-01-24-17/+18
| | | | | | | | The watchdog can be reset later when probing the LPC after relocation. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move graphics init much laterSimon Glass2016-01-24-78/+76
| | | | | | | | We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Probe the LPC in CPU initSimon Glass2016-01-24-3/+2
| | | | | | | | We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Rename lpc_init() to lpc_init_extra()Simon Glass2016-01-24-3/+3
| | | | | | | | In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move LPC and PCH init into northbridge probe()Simon Glass2016-01-24-23/+24
| | | | | | | Move more code into the northbridge probe() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge init into the probe() methodSimon Glass2016-01-24-14/+21
| | | | | | | | Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add a driver for the bd82x6x northbridgeSimon Glass2016-01-24-0/+25
| | | | | | | | Add a driver with an empty probe function where we can move init code in follow-on patches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Add a northbridge uclassSimon Glass2016-01-24-0/+17
| | | | | | | | Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Rename bd82x6x_init()Simon Glass2016-01-24-3/+11
| | | | | | | | Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move more init to the probe() functionSimon Glass2016-01-24-43/+43
| | | | | | | | Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_early_init() to probe()Simon Glass2016-01-24-28/+26
| | | | | | | | Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the LPC device using driver modelSimon Glass2016-01-24-1/+15
| | | | | | | | | | Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Convert bios_emu to use the driver model PCI APISimon Glass2016-01-24-8/+165
| | | | | | | | At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: syscon: Allow finding devices by driver dataSimon Glass2016-01-24-12/+50
| | | | | | | | We have a way to find a regmap by its syscon driver data value. Add the same for syscon itself. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: usb: Add a compatible string for PCI EHCI controllerSimon Glass2016-01-24-0/+6
| | | | | | | | | Add a compatible string to allow this to be specified in the device tree if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Display the error number when driver binding failsSimon Glass2016-01-24-1/+2
| | | | | | | | This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not compiled in. Display the error number to make this easier to spot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Drop the weak cpu_irq_init() functionSimon Glass2016-01-24-17/+0
| | | | | | | | There are no callers now. Platforms which need to set up interrupts their own way can implement an interrupt driver. Drop this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: queensbay: Add an interrupt driverSimon Glass2016-01-24-39/+67
| | | | | | | | | Add a driver for interrupts on queensbay and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: quark: Add an interrupt driverSimon Glass2016-01-24-27/+51
| | | | | | | | | Add a driver for interrupts on quark and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop the irq router compatible stringSimon Glass2016-01-24-2/+0
| | | | | | | We use driver model for this now, so we don't need this string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use the IRQ device when setting up the mptableSimon Glass2016-01-24-19/+11
| | | | | | | | | Instead of searching for the device tree node, use the IRQ device which has a record of it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Add a common PIRQ init functionSimon Glass2016-01-24-1/+13
| | | | | | | | | Most x86 interrupt drivers will want to use the standard PIRQ routing and table setup. Put this code in a common function so it can be used by those drivers that want it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Set up interrupt routing from interrupt_init()Simon Glass2016-01-24-26/+12
| | | | | | | | | | | | | | | At present interrupt routing is set up from arch_misc_init(). We can do it a little later instead, in interrupt_init(). This removes the manual pirq_init() call. Where the platform does not have an interrupt router defined in its device tree, no error is generated. Some platforms do not have this. Drop pirq_init() since it is no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Create a driver for x86 interruptsSimon Glass2016-01-24-0/+26
| | | | | | | | | | | | | | | | It seems likely that at some point we will want a generic interrupt uclass. But this is a big undertaking as it involves unifying code across multiple architectures. As a first step, create a simple IRQ uclass and a driver for x86. This can be generalised later as required. Adjust pirq_init() to probe this driver, which has the effect of creating routing tables and setting up the interrupt routing. This is a start towards making interrupts fit better with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-24-442/+461
| | | | | | | | | | | | | | | | | | | | | | | | | At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Separate out the read/write trace from normal debuggingSimon Glass2016-01-24-9/+15
| | | | | | | | | The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important init and error debug messages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Add a driver for Intel PCH9Simon Glass2016-01-24-0/+44
| | | | | | | | | At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH9. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Add a driver for Intel PCH7Simon Glass2016-01-24-0/+66
| | | | | | | | | At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Expand the uclass for Platform Controller Hubs (PCH)Simon Glass2016-01-24-1/+112
| | | | | | | | | | | | | | A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Avoid using pci_bus_to_hose() in the uclassSimon Glass2016-01-24-7/+7
| | | | | | | | | This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to write a BARSimon Glass2016-01-24-2/+23
| | | | | | | | Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move pci_bus_to_hose() to compatibilitySimon Glass2016-01-24-15/+28
| | | | | | | | This function should not be used by driver-model code, so move it to the compatibility portion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2016-01-22-1/+1
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| * devicetree: use wildcard to clean arch subdirThomas Chou2016-01-22-1/+1
| | | | | | | | | | | | | | | | Use wildcard to clean arch subdirectories, as it is cleaner than listing all the arch which builds dtb. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | rockchip: Update the READMESimon Glass2016-01-21-20/+20
| | | | | | | | | | | | | | | | | | | | GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC. There is an implementation to run the CPU at full speed although it does not seem to make much difference. Update the README to cover recent developments. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add support for Raxda Rock 2Simon Glass2016-01-21-6/+133
| | | | | | | | | | | | | | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rock2: dts: Make changes for U-BootSimon Glass2016-01-21-0/+21
| | | | | | | | | | | | Add the required pre-relocation tags and SDRAM init information for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rock2: Bring in device tree files from LinuxSimon Glass2016-01-21-0/+458
| | | | | | | | | | | | | | Bring in the current device tree files for rock2 from linux/next commit 719d6c1. Hopefully this is the latest one. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: dts: Sync up SPDIF node with LinuxSimon Glass2016-01-21-0/+21
| | | | | | | | | | | | | | This has been added and we have references to it in the rock2 board. Add this node. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: firefly-rk3288: Enable HDMI outputSimon Glass2016-01-21-1/+15
| | | | | | | | | | | | Enable HDMI output and a console on firefly. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-14 22:16:52 +0000