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| * | | spi: cadence_qspi: Ensure check for max frequency in placeChin Liang See2015-11-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure the intended SCLK frequency not exceeding the maximum frequency. If that happen, SCLK will set to maximum frequency. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | spi: cadence_qspi: Fix fdt read of spi-max-frequencyChin Liang See2015-11-05-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | spi: cadence_qspi: Ensure spi_calibration is run when sclk changeChin Liang See2015-11-05-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | | lib, fdt: Adding fdtdec_get_uint functionChin Liang See2015-11-05-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding fdtdec_get_uint function which is the unsigned version for fdtdec_get_int Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Heiko Schocher <hs@denx.de>
| * | | arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit definesDinh Nguyen2015-11-03-3/+3
| |/ / | | | | | | | | | | | | | | | | | | The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-11-04-1/+1845
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| * | | mpc85xx: Add support for the Varisys Cyrus boardAndy Fleming2015-11-04-0/+1810
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS. Large amounts of this code were developed by Adrian Cox <adrian at humboldt dot co dot uk> Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | rtc: Add MCP79411 support to DS1307 rtc driverAndy Fleming2015-11-04-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is from Adrian Cox, and is patterned after similar support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This chip is used on the Cyrus board from Varisys. Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ARM: zynq: Remove zc70x targetMichal Simek2015-11-04-34/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove zc70x target which was one setting for zc702 and zc706. Currently zc702 and zc706 are separated. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | arm: zynq: Move serial driver to driver modelSimon Glass2015-11-04-113/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use driver model and change all users. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: serial: Drop non-device-tree serial driver portionsSimon Glass2015-11-04-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we use device tree in SPL also, we can drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | ARM: zynqmp: Enable DM and OF bindingMichal Simek2015-11-04-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI requires DM and OF that's why enable DM for ZynqMP and start to use configuration based on embedded OF. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | arm: zynq: dts: Add U-Boot device tree additionsSimon Glass2015-11-04-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to mark some device tree nodes so that they are available before relocation. This enables driver model to find these automatically. In the case of SPL it ensures that these nodes will be retained in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | dm: arm: zynq: Enable device tree control in SPLSimon Glass2015-11-04-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to using device tree control in SPL so that we can use the same driver code in both SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: Support the debug UARTSimon Glass2015-11-04-16/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the debug UART to assist with early debugging. Enable it for Zybo as an example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: Drop unnecessary code in SPL board_init_f()Simon Glass2015-11-04-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to the new way of starting up SPL. Clearing of BSS and calling board_init_r() is now handled by crt0.S. Also tidy up the header include order. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: Use separate device tree instead of embeddedSimon Glass2015-11-04-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Production boards should not use CONFIG_OF_EMBED. Fix this for the Zybo boards. The image to use now becomes u-boot-dtb.bin. For example, the .bif file should contain a line like: [load = 0x04000000,startup=0x04000000]/path/to/u-boot-dtb.bin instead of: [load = 0x04000000,startup=0x04000000]/path/to/u-boot.bin When device tree is enabled we need to load u-boot-dtb.img. Change the settings so that SPL does the right thing. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | dm: spl: Support device tree when BSS is in a different sectionSimon Glass2015-11-04-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present in SPL we place the device tree immediately after BSS. This avoids needing to copy it out of the way before BSS can be used. However on some boards BSS is not placed with the image - e.g. it can be in RAM if available. Add an option to tell U-Boot that the device tree should be placed at the end of the image binary (_image_binary_end) instead of at the end of BSS. Note: A common reason to place BSS in RAM is to support the FAT filesystem. We should update the code so that it does not use so much BSS. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | dm: spl: Generate u-boot-spl-dtb.bin only when enabledSimon Glass2015-11-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this file is generated even when device tree is not enabled in SPL. Avoid this, since this file serves no purpose in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | dm: serial: Deal with stdout-path with an aliasSimon Glass2015-11-04-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes stdout-path contains a UART alias along with speed, etc. For example: stdout-path = "serial0:115200n8"; Add support for decoding this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | fdtgrep: Simplify the alias generation codeSimon Glass2015-11-04-22/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need to allocate a new region list when we run out of space. The outer function can take care of this for us. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | fdt: Correct handling of alias regionsSimon Glass2015-11-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the last four bytes of the alias region are dropped in the case where the last alias is included. This results in a corrupted device tree. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | fdt: Add a function to look up a /chosen propertySimon Glass2015-11-04-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is sometimes useful to find a property in the chosen node. Add a function for this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | ARM: zynqmp: Add DTS for ep108 boardMichal Simek2015-11-04-0/+963
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DTS for ep108 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot
* | | | zynq-common: Define CONFIG_SYS_I2C_ZYNQ based on board configSiva Durga Prasad Paladugu2015-11-04-0/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_SYS_I2C_ZYNQ only if it has either I2C0 or I2C1 enabled in a board config.This fixes the issue of i2c error during board init if board specific doesnt have either I2C0 or I2C1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | arm: at91: reworked meesc board supportDaniel Gorsulowski2015-11-03-26/+36
| | | | | | | | | | | | Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* | | mmc: atmel: Add atmel sdhci supportWenyou Yang2015-11-03-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: clock: Add the generated clock supportWenyou Yang2015-11-03-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some peripherals may need a second clock source that may be different from the system clock. This second clock is the generated clock (GCK) and is managed by the PMC via PMC_PCR. For simplicity, the clock source of the GCK is fixed to PLLA_CLK. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | mmc: sdhci: Fix the SD clock stop sequenceWenyou Yang2015-11-03-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the SDHC specification, stopping the SD Clock is by setting the SD Clock Enable bit in the Clock Control register at 0, instead of setting all bits at 0. Before stopping the SD clock, we need to make sure all SD transactions to complete, so add checking the CMD and DAT bits in the Presen State register, before stopping the SD clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | | arm: at91: Change the Chip ID registers' addressesWenyou Yang2015-11-03-7/+10
|/ / | | | | | | | | | | | | | | Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1Shengzhou Liu2015-11-02-1/+2
| | | | | | | | | | | | | | | | T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing for PLL ratio. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | T104xD4RDB: Fix PHY address for PHY connected to FM1@DTSEC3Codrin Ciubotariu2015-11-02-1/+3
| | | | | | | | | | | | | | | | | | On T1040D4RDB board, u-boot fails to connect port FM1@DTSEC3 to the Ethernet PHY because the wrong PHY address is used. Also, T1040D4RDB supports SGMII on one port only. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter CardYangbo Lu2015-11-02-0/+6
| | | | | | | | | | | | | | | | | | When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/t1040qds: enable peripheral clock for eSDHCYangbo Lu2015-11-02-0/+1
| | | | | | | | | | Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/t1040qds: enable adapter card type identification supportYangbo Lu2015-11-02-0/+1
| | | | | | | | | | Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter CardYangbo Lu2015-11-02-0/+5
| | | | | | | | | | | | | | | | If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Powerpc: eSDHC: expand a fix to T4160Shaohui Xie2015-11-02-1/+2
| | | | | | | | | | | | | | | | commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board", T4160 also needs this fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdmZhao Qiang2015-11-02-0/+33
| | | | | | | | | | | | | | | | | | qe-tdm is muxed with diu, if hwconfig setted as qe-tdm, assign muxed pins to qe-tdm, then delete diu node from device tree. Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ARM: at91: sama5: change the environment address to 0x6000Josh Wu2015-11-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As sama5 board has 32k sram size, so the at91bootstrap and spl for sama5 boards is bigger than 16k (0x4000). That will overlap the U-Boot environment. So I move environment to 0x6000. And reduce its size as well. Following shows the size of the spl binaries (v2015.04 vs v2015.07): % ls v2015.04/*spi*spl.bin -l | awk '{print $5,$(NF)}' 15540 v2015.04/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin 15704 v2015.04/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin 16064 v2015.04/sama5d3xek_spiflash_defconfig_u-boot-spl.bin 16304 v2015.04/sama5d4ek_spiflash_defconfig_u-boot-spl.bin 16304 v2015.04/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin % ls v2015.07/*spi*spl.bin -l | awk '{print $5,$(NF)}' 16136 v2015.07/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin 16300 v2015.07/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin 16664 v2015.07/sama5d3xek_spiflash_defconfig_u-boot-spl.bin 16904 v2015.07/sama5d4ek_spiflash_defconfig_u-boot-spl.bin 16904 v2015.07/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin The gcc version is: gcc 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1) Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Bo Shen <voice.shen@gmail.com>
* | lcd: atmel: Add 32bpp support for HLCDCMarek Vasut2015-11-01-0/+4
| | | | | | | | | | | | | | | | Add 32bpp framebuffer support for the Atmel HLCDC driver. This is needed for output bpp higher than 16bpp. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Zap global 'initialized' variableMarek Vasut2015-11-01-4/+4
| | | | | | | | | | | | | | | | | | Global variables are bad. Get rid of this particular one, so we can correctly instantiate multiple atmel mci interfaces, without having them interfere with one another. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Implement proper private dataMarek Vasut2015-11-01-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | Instead of passing just the register area as a private data, introduce a proper struct atmel_mci_priv structure instead. This will become useful in the subsequent patch, where we eliminate the global variable from this driver. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fix free()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Fix clock configurationMarek Vasut2015-11-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | After silencing the prints which were generated when reconfiguring the clock of the SD/MMC bus, surprisingly, the driver stopped working such that every attempt to use the SD/MMC bus caused the CPU to get totally stuck hard. It turns out that the prints generated a short delay, which was necessary for the CPU to reconfigure the clock without getting stuck. Thus, this patch adds a short delay after the clock configuration instead. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Silence debug outputMarek Vasut2015-11-01-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver generates clearly debugging prints when changing clock speed, so silence those. Furthermore, the driver generates further prints in case a command fails to complete. The later case woud be useful, but for eMMC, command 8 can fail and it's not an error but a part of the specification. Thus, make this debug() as well. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: simplify spl board_init_f functionJosh Wu2015-11-01-5/+0
|/ | | | | | | | | crt0.S do both memset the bss section and call board_init_r for us, so remove them from board_init_f(). Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* x86: Select the ns16550 debug UART for minnowmax, chromebook_linkSimon Glass2015-10-30-0/+2
| | | | | | | At present the debug UART is not selected which causes a build error. Correct this. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-1091/+4390
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| * ls102xa: Adjust some macros for SD boot on LS1021A QDS boardAlison Wang2015-10-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As more features are added for SD boot on LS1021A QDS board, the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS needs to be adjusted to a suitable value. Starting address of the malloc pool used in SPL needs to be adjusted too, or it will occupy the address u-boot loads. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * configs: ls1021atwr: Enable ID EEPROM for SD bootYao Yuan2015-10-30-2/+0
| | | | | | | | | | | | | | | | I2C1 can work on ls102xa rev2.0 SD boot, so add ID EEPROM for SD boot. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021atwr: optimize the deep sleep latencytang yuantian2015-10-30-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | It will take more than 1s when wake up from deep sleep. Most of the time is spent on outputing information. This patch reduced the deep sleep latency by: 1. avoid outputing system informaton 2. remove flush cache after DDR restore 3. skip reloading second stage uboot binary when SD boot Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-07 15:45:09 +0000