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* | ARM: keystone2: Remove unsed external clocksLokesh Vutla2015-08-12-66/+15
| | | | | | | | | | | | | | | | Remove unused external clocks and make a common definition for all keystone platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: keystone2: Cleanup init_pll definitionLokesh Vutla2015-08-12-46/+84
| | | | | | | | | | | | | | | | | | This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: keystone2: Use common structure for PLLsLokesh Vutla2015-08-12-51/+22
| | | | | | | | | | | | | | | | | | | | Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: keystone2: Fix dev and arm speed detectionLokesh Vutla2015-08-12-162/+114
| | | | | | | | | | | | | | | | | | Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: keystone2: Cleanup PLL init codeLokesh Vutla2015-08-12-174/+211
| | | | | | | | | | | | | | | | | | | | | | There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFOLokesh Vutla2015-08-12-0/+33
| | | | | | | | | | | | | | | | | | | | Add print_cpuinfo() function and enable CONFIG_DISPLAY_CPUINFO for keystone platforms, so that cpu info can be displayed during boot. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: keystone2: Cleanup SoC detectionLokesh Vutla2015-08-12-16/+26
| | | | | | | | | | | | | | | | | | Add proper register definition for JTAG ID and cleanup cpu_is_* functions. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA72: disable workaround for 801819Nishanth Menon2015-08-12-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA72x processor variants are single core and it does not export ACP[1]. Hence, we have no source for generating an external snoop requests which appear to be key to the deadlock in DRA72x design. Since we build the same image for DRA74x and DRA72x platforms, lets runtime detect and disable the workaround (in favor of performance) on DRA72x platforms. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | ARM: DRA7/ OMAP5: implement Auxiliary Control Register configurationNishanth Menon2015-08-12-0/+7
| | | | | | | | | | | | | | | | | | | | Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | ARM: Introduce erratum workaround for 801819Nishanth Menon2015-08-12-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for Cortex-A15 ARM erratum 801819 which says in summary that "A livelock can occur in the L2 cache arbitration that might prevent a snoop from completing. Under certain conditions this can cause the system to deadlock. " Recommended workaround is as follows: Do both of the following: 1) Do not use the write-back no-allocate memory type. 2) Do not issue write-back cacheable stores at any time when the cache is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it is implementation defined whether cacheable stores update the cache when the cache is disabled it is not expected that any portable code will execute cacheable stores when the cache is disabled. For implementations of Cortex-A15 configured without the “L2 arbitration register slice” option (typically one or two core systems), you must also do the following: 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111 So, we provide an option to disable write streaming on OMAP5 and DRA7. It is a rare condition to occur and may be enabled selectively based on platform acceptance of risk. Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3] is set to 0. Note: certain unicore SoCs *might* not have REVIDR[3] not set, but might not meet the condition for the erratum to occur when they donot have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency Extensions). Such SoCs will need the work around handled in the SoC specific manner, since there is no ARM generic manner to detect such configurations. Based on ARM errata Document revision 18.0 (22 Nov 2013) Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | integrator: switch to DM serial portLinus Walleij2015-08-12-20/+28
| | | | | | | | | | | | | | | | This switches the Integrator boards over to using the device model for its serial ports. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | usb: ohci: enable cache supportWu, Josh2015-08-12-12/+2
| | | | | | | | | | | | | | | | Remove the CONFIG_DM_USB limitation to enable cache support functions. Tested on SAMA5D3x-EK board. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-60/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* | ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-32/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | m68k: cache: add an empty stub functions for invalidate/flush dcacheWu, Josh2015-08-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But m68k don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all m68k cpu. Also each cpu can implement its own implementation. If not implemented then by default is using an empty function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Angelo Dureghello <angelo@sysam.it>
* | Correct License and Copyright information on few filesRuchika Gupta2015-08-12-4/+7
| | | | | | | | | | | | | | | | | | gpio.h - Added missing copyright in few files. rsa-mod-exp.h - Corrected copyright in the file. fsl_sec.h - Added missing license in files drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
* | ti: drop value from CONFIG_SYS_NAND_BUSWIDTH_16BITStefano Babic2015-08-12-12/+12
| | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | mcx: add Ethernet over USBStefano Babic2015-08-12-0/+3
| | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap3: fix NAND support for mcx boardStefano Babic2015-08-12-0/+3
| | | | | | | | | | | | | | | | mcx was not updated according to changes in NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers: hierarchize drivers Kconfig menuMasahiro Yamada2015-08-12-0/+68
| | | | | | | | | | | | | | | | | | | | | | The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
* | include/bitfield.h: Assure new bitfield value doesn't touch unwanted bitsCodrin Ciubotariu2015-08-12-1/+1
| | | | | | | | | | | | | | The new bitfield value must not be higher than its mask. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | arm/rpi: Enable dcacheAlexander Stein2015-08-12-1/+1
| | | | | | | | | | | | | | | | | | Now that mailbox driver supports cache flush and invalidation, we can enable dcache. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | dwc2: Add dcache supportAlexander Stein2015-08-12-7/+17
| | | | | | | | | | | | | | | | | | | | | | This adds dcache support for dwc2. The DMA buffers must be DMA aligned and is flushed for outgoing transactions before starting transfer. For ingoing transactions it is invalidated after the transfer has finished. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> [trini: Update to apply again on top of DM patches] Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailboxAlexander Stein2015-08-12-0/+12
| | | | | | | | | | | | | | | | | | | | When using dcache the setup data for the mailbox must be actually written into memory before calling into firmware. Thus flush and invalidate the memory. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: bcm283x: Allocate all mailbox buffers cacheline alignedAlexander Stein2015-08-12-7/+7
| | | | | | | | | | | | | | | | | | | | The mailbox buffer is required to be at least 16 bytes aligned, but for cache invalidation and/or flush it needs to be cacheline aligned. Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZEAlexander Stein2015-08-12-0/+3
| | | | | | | | | | | | | | | | | | | | The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | arm1136/arm1176: Merge cache handling codeAlexander Stein2015-08-12-53/+12
| | | | | | | | | | | | | | | | | | | | | | As both cores are similar merge the cache handling code for both CPUs to arm11 directory. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> [trini: Add hunk to arch/arm/cpu/arm1136/Makefile] Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm1136: Remove dead codeAlexander Stein2015-08-12-10/+0
| | | | | | | | | | | | | | | | | | Apparently lcd_panel_disable is not defined anywhere, so no config for an arm1136 board would have set CONFIG_LCD. Remove the unused code. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | sniper: Keypad support, with recovery and fastboot key combinationsPaul Kocialkowski2015-08-12-0/+16
| | | | | | | | | | | | | | | | | | | | | | Using the twl4030 keypad allows booting directly into some special boot modes, such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while the VOL- key will trigger a boot to fastboot. The G (gesture) key remains unused at this point. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sniper: Power off when the power on reason is not a valid onePaul Kocialkowski2015-08-12-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In most cases, userspace will attempt to power off the device with HALT instead of POWER_OFF, which triggers a reset instead of a proper power off from the TWL4030. Hence, it is up to the bootloader to actually turn the device off when there is no reason to turn it on. A reboot identified with the OMAP reboot mode bits set is acceptable, as well as a power on reason from either the power button, USB or charger plug. Other cases should trigger a power off. Note that for the U-Boot reset command to take effect, we have to fill-in the OMAP reboot bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sniper: Power button reset supportPaul Kocialkowski2015-08-12-0/+4
| | | | | | | | | | | | | | This adds support for resetting the device on a long press on the power button. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sniper: Fastboot supportPaul Kocialkowski2015-08-12-0/+70
| | | | | | | | | | | | | | | | | | | | This adds support for the fastboot USB gadget, including flashing to the internal MMC and reboot to bootloader or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Update to use Kconfig for MUSB] Signed-off-by: Tom Rini <trini@konsulko.com>
* | sniper: Pass serial number through ATAGPaul Kocialkowski2015-08-12-0/+19
| | | | | | | | | | | | | | | | | | Now that the serial number is correctly defined, we can pass it to the kernel using the (legacy) ATAG method. It will be automatically passed via device-tree when enabled. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sniper: Serial number support, obtained from die IDPaul Kocialkowski2015-08-12-0/+13
| | | | | | | | | | | | | | The OMAP3 has some die-specific ID bits that we can use to give the device a (more or less) unique serial number. This is particularly useful for e.g. USB. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | sniper: OMAP3 reboot mode supportPaul Kocialkowski2015-08-12-0/+21
| | | | | | | | | | | | | | | | | | This adds support for the omap3 reboot mode mechanism and exports the reboot mode via an environment variable, that is used in the boot command to make it possible to boot from the recovery partition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | LG Optimus Black (P970) codename sniper supportPaul Kocialkowski2015-08-12-0/+758
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LG Optimus Black (P970) codename sniper is a smartphone that was designed and manufactured by LG Electronics (LGE) and released back in 2011. It is using an OMAP3630 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. This port is aimed at running an Android version such as Replicant, the fully free Android distribution. However, support for upstream Linux with device-tree and common GNU/Linux distros boot commands could be added in the future. For more information about the journey to freeing this device, please read the series of blog posts at: http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add CONFIG_OF_SUPPORT] Signed-off-by: Tom Rini <trini@konsulko.com>
* | omap3: Reboot mode supportPaul Kocialkowski2015-08-12-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Reboot mode is written in scratchpad memory before reboot in the form of a single char, that is the first letter of the reboot mode string as passed to the reboot function. This mechanism is supported on OMAP3 both my the upstream kernel and by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | input: twl4030: Keypad scan and inputPaul Kocialkowski2015-08-12-0/+42
| | | | | | | | | | | | | | | | | | | | | | This allows scanning the twl4030 keypad, storing the result in a 64-byte long matrix with the twl4030_keypad_scan function. Detecting a key at a given column and row is made easier with the twl4030_keypad_key function. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | input: TWL4030 input support for power button, USB and chargerPaul Kocialkowski2015-08-12-0/+64
| | | | | | | | | | | | | | This adds support for detecting a few inputs exported by the TWL4030. Currently-supported inputs are the power button, USB and charger presence. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | power: twl4030: Power off supportPaul Kocialkowski2015-08-12-8/+84
| | | | | | | | | | | | | | | | | | | | This adds support for powering off (the omap3 SoC) from the twl4030. This is especially useful when the kernel does not actually power off the device using this method but reboots and leaves it up to the bootloader to actually turn the power off. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | lpc32xx: devkit3250: add spl build supportVladimir Zapolskiy2015-08-12-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND. All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | lpc32xx: devkit3250: update of board configurationVladimir Zapolskiy2015-08-12-6/+120
| | | | | | | | | | | | | | | | | | | | | | | | This change adds more peripherals to Timll DevKit3250 board, namely MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C. Also the default serial console is changed to UART5, added an option to pass device tree blob by means of bootm, predefined environment variables are slightly extended and reserved space on NAND to store user defined U-boot environment. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-12-0/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* | spl: nand: simple: replace readb() with chip specific read_buf()Vladimir Zapolskiy2015-08-12-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework. NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | image: fix Android ramdisk support when dtb is specifiedRob Herring2015-08-12-10/+8
| | | | | | | | | | | | | | | | | | If a dtb is specified on the command-line, the Android boot image ramdisk will not be found. Fix this so that we can specify the ramdisk address and dtb address. The syntax is to enter the Android boot image address for both the kernel and ramdisk. Signed-off-by: Rob Herring <robh@kernel.org>
* | JFFS2: Use merge sort when parsing filesystemMark Tomlinson2015-08-12-35/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | When building the file system the existing code does an insertion into a linked list. It attempts to speed this up by keeping a pointer to where the last entry was inserted but it's still slow. Now the nodes are just inserted into the list without searching through for the correct place. This unsorted list is then sorted once using mergesort after all the entries have been added to the list. This speeds up the scanning of the flash file system considerably. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
* | JFFS2: Use CLEANMARKER to reduce scanning timeMark Tomlinson2015-08-12-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | If a sector has a CLEANMARKER at the beginning, it indicates that the entire sector has been erased. Therefore, if this is found, we can skip the entire block. This was not being done before this patch. The code now does the same as the kernel does when encountering a CLEANMARKER. It still checks that the next few words are FFFFFFFF, and if so, the block is assumed to be empty, and so is skipped. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
* | JFFS2: Change scansize to match linux kernelMark Tomlinson2015-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The scan code is similar to the linux kernel, but the kernel defines a much smaller size to scan through before deciding a sector is blank. Assuming that what is in the kernel is OK, make these two match. On its own, this change makes no difference to scanning of any sectors which have a clean marker at the beginning, since the entire sector is not blank. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
* | JFFS2: Optimize building lists during scanMark Tomlinson2015-08-12-4/+21
| | | | | | | | | | | | | | If the flash is slow, reading less from the flash into buffers makes the process faster. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
* | JFFS2: Improve speed reading flash filesMark Tomlinson2015-08-12-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | jffs2_1pass_read_inode() would read the entire data for each node in the filesystem, regardless of whether it was part of the file to be loaded or not. By only reading the header data for an inode, and then reading the data only when it is found to be part of the file to be loaded, much copying of data is saved. jffs2_1pass_list_inodes() read each inode for every file in the directory into a buffer. By using NULL as a buffer pointer, NOR flash simply returns a pointer, and therefore avoids a memory copy. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
generated by cgit v1.1 at 2024-11-15 13:52:36 +0000