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| * powerpc/85xx: Fix e6500 L2 cache stash IDsScott Wood2014-04-22-4/+8
| | | | | | | | | | | | | | | | The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/phy: Fix PHY id for VSC8514Codrin Ciubotariu2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/fsl_ifc: Add a function to finalize CS0 address bindingYork Sun2014-04-22-0/+8
| | | | | | | | | | | | | | | | | | For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * board/b4860qds:Slow MDC clock to comply IEEE specs in PBI configPrabhakar Kushwaha2014-04-22-0/+3
| | | | | | | | | | | | | | | | | | | | The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * t1040rdb/qe: add QE support for T1040RDBZhao Qiang2014-04-22-0/+4
| | | | | | | | | | | | | | | | add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into "include/configs/T1040RDB.h" Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * QE/U-QE: Add U-QE supportZhao Qiang2014-04-22-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-61/+66
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDBAneesh Bansal2014-04-22-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDSAneesh Bansal2014-04-22-1/+4
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDSAneesh Bansal2014-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDSAneesh Bansal2014-04-22-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add NAND secure boot target for BSC9132QDSAneesh Bansal2014-04-22-1/+10
| | | | | | | | | | | | | | | | | | | | In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDSAneesh Bansal2014-04-22-7/+12
| | | | | | | | | | | | | | | | | | | | Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platformsAneesh Bansal2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399Aneesh Bansal2014-04-22-2/+1
| | | | | | | | | | | | | | | | | | The workaround for IFC errata A003399 was not enabled in case of secure boot. So, secure boot from NOR was not working. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/p1010rdb: SECURE BOOT enabled for NANDAneesh Bansal2014-04-22-1/+2
| | | | | | | | | | | | | | | | | | | | In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/usb: Fix phy type for Second USB controllerNikhil Badola2014-04-22-2/+6
| | | | | | | | | | | | | | | | | | Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: Nikhil Badola <B46172@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-4/+592
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC 85xx: Add ELF entry pointAlexander Graf2014-04-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC: 85xx: Generalize DDR TLB mapping functionAlexander Graf2014-04-22-15/+40
| | | | | | | | | | | | | | | | | | | | The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC: 85xx: Remove IVOR resetAlexander Graf2014-04-22-101/+5
| | | | | | | | | | | | | | | | | | | | | | There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
| * fdt_support: Add helper function to read "ranges" propertyAlexander Graf2014-04-22-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a helper function that can be used to interpret most "ranges" properties in the device tree. It reads the n'th range out of a "ranges" array and returns the node's virtual address of the range, the physical address that range starts at and the size of the range. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fdt_support: split fdt_getprop_u32_defaultAlexander Graf2014-04-22-6/+34
| | | | | | | | | | | | | | | | | | | | We already have a nice helper to give us a property cell value with default fall back from a path. Split that into two helpers - one for the old path based lookup and one to give us a value based on a node offset. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2014-04-23-6119/+83
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| * | MAKEALL: remove hard-coded MIPS boardsDaniel Schwierzeck2014-04-20-39/+1
| | | | | | | | | | | | | | | | | | | | | Remove all MIPS boards and use $(targets_by_arch mips) for filling list_MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: drop incaip boardDaniel Schwierzeck2014-04-20-5201/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
| * | MIPS: Malta: convert to generic boardPaul Burton2014-04-20-0/+3
| | | | | | | | | | | | | | | | | | | | | This patch converts the MIPS Malta development board to make use of the generic board code now that it is supported on MIPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: allow use of generic boardPaul Burton2014-04-20-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | This patch allows MIPS boards to make use of generic board, replacing arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with the asm-generic version. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | board_f: call timer_init on MIPSPaul Burton2014-04-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | MIPS needs a call to timer_init to preserve its current behaviour ensuring that the cop0 compare register is initialised appropriately. Reported-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | board_f: call init_func_ram on MIPSPaul Burton2014-04-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Assigning gd->ram_size the return value of initdram matches the existing MIPS board behaviour. Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: define __init_end in u-boot.ldsPaul Burton2014-04-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The generic board code uses the __init_end symbol to calculate monitor_flash_len. Define said symbol for MIPS, equivalent to __image_copy_end which is used for the same purpose in arch/mips/lib/board.c. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: move mips_io_port_base out of board.cPaul Burton2014-04-20-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | Move the definition of this variable out of arch/mips/lib/board.c in preparation for allowing use of generic board on MIPS, which will lead to this file not being compiled. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: stub interrupt_init functionPaul Burton2014-04-20-0/+10
| | | | | | | | | | | | | | | | | | | | | interrupt_init is called unconditionally by the generic board code. Define a stub for it on MIPS like the enable & disable functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | cosmetic: README: add some entries to Directory HierarchyMasahiro Yamada2014-04-20-0/+5
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | mips: xburst: remove remainders of dead boardMasahiro Yamada2014-04-20-843/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 54e458de deleted qi_lb60 board support because of the incompatible license issue. There is no board with XBurst CPU. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: always keep all sections in u-boot ELF binary.Daniel Schwierzeck2014-04-20-27/+32
| |/ | | | | | | | | | | | | | | Always keep all sections in u-boot ELF binary. Move all unneeded sections after _end to avoid allocating space in the final binary. Also remove .deadcode section which is now obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Revert "build: Use filechk rules to create and update u-boot.lds"Masahiro Yamada2014-04-23-5/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a8b993eb81c142a439c24b871a2317f765fe5397. Commit a8b993eb claims it fixes u-boot.lds rule by replacing $(call if_changed) with $(call filechk). But the problem had already been fixed by commit 395e60cd a few days before commit a8b993eb was posted. There is no reason to apply commit a8b993eb. What is worse is $(call filechk) is too strong to fix the problem and looks weird. Date of the two patches: [1] commit 395e60cdc292dc0183c6867d34b43f14a373df55 Author: Masahiro Yamada <yamada.m@jp.panasonic.com> AuthorDate: Wed Apr 9 20:10:43 2014 +0900 Commit: Tom Rini <trini@ti.com> CommitDate: Fri Apr 11 10:08:42 2014 -0400 replaces $(call if_changed) -> $(call if_changed_dep) [2] commit a8b993eb81c142a439c24b871a2317f765fe5397 Author: Jon Loeliger <jon.loeliger@oracle.com> AuthorDate: Tue Apr 15 16:09:37 2014 -0500 Commit: Tom Rini <trini@ti.com> CommitDate: Fri Apr 18 16:14:16 2014 -0400 replaces $(call if_changed) -> $(call filechk) A conflict must have happened when applying [2], but somehow it was applied, sadly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jon Loeliger <jon.loeliger@oracle.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com>
* ARM:tegra20: Remove aes debug printsTom Rini2014-04-18-9/+0
| | | | | | | | In 6e7b9f4 some of the debug prints for AES code moved into the generic code, so we remove these additional calls. Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Tom Warren <twarren@nvidia.com>
* aes: make apply_cbc_chain_data non-staticStephen Warren2014-04-18-14/+16
| | | | | | | | | | | | | | | | | | Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart code. This function was recently moved into the core aes.c and made static, which prevents the Tegra code from compiling. Make it public again to avoid the compile errors: arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’: arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration] arch/arm/cpu/built-in.o: In function `sign_object': .../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data' .../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data' Fixes: 6e7b9f4fa0ae ("aes: Move the AES-128-CBC encryption function to common code") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* build: Use filechk rules to create and update u-boot.ldsJon Loeliger2014-04-18-4/+5
| | | | | | | | | | | | | Prior to this patch, the top-level linker script u-boot.lds used a simple $(call if_changed) check when generated. That mechanism misses cases where a possible include file change induces a change in the u-boot.lds too. This patch converts it to a stronger check using ($call filechk) that will also notice differences in file contents and will catch changes due to pre-processing as well. Signed-off-by: Jon Loeliger <jon.loeliger@oracle.com>
* buildman: make output dir configurableDaniel Schwierzeck2014-04-18-1/+4
| | | | | | | | Add an option to specify the output directory to override the default path '../'. This is useful for building in a ramdisk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* e1000: remove redundant assignmentDavid Müller (ELSOFT AG)2014-04-18-1/+0
| | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* bootm: set max decompression size for LZOKees Cook2014-04-18-1/+1
| | | | | | | | | | The LZO decompressor wasn't initializing the maximum output size, which meant it would fail to decompress most of the time. Reported-by: Matthias Weißer <weisserm@arcor.de> Signed-off-by: Kees Cook <keescook@chromium.org> Tested-by: Matthias Weißer <weisserm@arcor.de> Acked-by: Simon Glass <sjg@chromium.org>
* kbuild: add user-supplied CPPFLAGS, AFLAGS and CFLAGSMasahiro Yamada2014-04-18-0/+5
| | | | | | | | Like Linux Kernel, this commit provides environment variables KCPPFLAGS, KAFLAGS and KCFLAGS, which are useful to pass additional options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: docbook: sync with Linux Kernel v3.15-rc1Masahiro Yamada2014-04-18-19/+10
| | | | | | | | | | | | | | | | | | | | This commit imports DocBook-related updates from v3.14 to v3.15-rc1. - commit ec3fadd64b9940baa2a369bf978e8561837db3f5 kbuild: docbook: use $(obj) and $(src) rather than specific path - commit 100da4c0150c97ce34d4d3b38bf2f5449b05ae4f kbuild: docbook: specify KERNELDOC dependency correctly - commit 6f89b9c1d6b29eaa600ac4a8ac1314b0d06f15e3 kbuild: docbook: include cmd files more simply - commit ac6d662a95a6989d83b259ccf8ec01dd7903af73 doc: Add "*.svg" to DocBook/.gitignore - commit 832919bfcf0cfd75767c68b0c61f7cf48be860a8 DocBook: Make mandocs parallel-safe - commit c4d79a4799719f2b0cd354ee498aad605730c97e work around xmlto bug in htmldocs Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: sync with Linux Kernel v3.15-rc1Masahiro Yamada2014-04-18-13/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit imports Kbuild-related updates from v3.14 to v3.15-rc1. - commit 3d3d6b8474204b6819688c9800774d52d370a538 kbuild: LLVMLinux: Adapt warnings for compilation with clang - commit 61163efae02040f66a95c8ed17f4407951ba58fa kbuild: LLVMLinux: Add Kbuild support for building kernel with Clang - commit 79192ca8ebd9a25c583aa46024a250fef1e7766f scripts: objdiff: detect object code changes between two commits - commit 1c9e70a55b088d97a59241744fe459409d0c3582 kbuild: create a build directory automatically for out-of-tree build - commit a03fcb50e816a69acffb13b5e56db75063aeba8a kbuild: remove redundant '.*.cmd' pattern from make distclean - commit 13338935f1574a2dcd1c891461b0dcc42f8cff42 kbuild: move "quote" to Kbuild.include to be consistent - commit bfdfaeae500a3b194b73b01e92a8034791a58b7f kbuild: specify build_docproc as a phony target - commit f4d4ffc03efc864645b990e1d579bbe1b8e358a4 kbuild: dtbs_install: new make target - commit 1e64ff42ea3d8d2fc8aa71f9717b3c1cb6c2f893 Kbuild, lto: Disable LTO for asm-offsets.c - commit ccbef1674a1579842c7dbdf554efca85d2cd245a Kbuild, lto: add ld-version and ld-ifversion macros - commit ae63b2d7bdd9bd66b88843be0daf8e37d8f0b574 scripts/tags.sh: Ignore *.mod.c - commit e36aaea28972c57a32a3ba5365e61633739719b9 kbuild: Fix silent builds with make-4 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* pcnet: force ordering of descriptor accessesPaul Burton2014-04-18-18/+19
| | | | | | | | | | | The ordering of accesses to the rx & tx descriptors is important, yet the send & recv functions accessed them via regular structure accesses. This leaves the compiler with the opportunity to reorder those accesses or to hoist them outside of loops. Prevent that from happening by using readl & writel to access the descriptors. As a nice bonus, this removes the need for the driver to care about endianness. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: align rx buffers for cache invalidationPaul Burton2014-04-18-9/+12
| | | | | | | | | | The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: access descriptor rings & init block uncachedPaul Burton2014-04-18-31/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | The prior accesses to the descriptor rings & init block via cached memory had a few issues: - The memory needs cache flushes or invalidation at the appropriate times, but was not necessarily aligned on cache line boundaries. This could lead to data being incorrectly lost or written back to RAM at the wrong time. - There are points where ordering of writes to the memory is important, but because it's cached memory the pcnet controller would see cache lines written back ordered by address. This could occasionally lead to hardware seeing descriptors in an incorrect state. - Flushing the cache constantly is inefficient. So, to avoid all of those issues simply access the descriptors & init block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is used to do this (retrieving an address in kseg1) as I could see no existing generic solution. Since the MIPS Malta board is the only user of the pcnet driver, hopefully this doesn't matter. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* doc:power:pmic: Add doc entry for PMIC(v2) frameworkŁukasz Majewski2014-04-18-0/+166
| | | | | | | | | | | Well written documentation for PMIC framework was missing and hence it has been probably difficult and time consuming for other developers to understand rationale for key design decisions and overall design structure. This commit provides proper documentation entry. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
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