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| * sunxi: enable SPL for sun9iPhilipp Tomsich2016-10-30-0/+1
| | | | | | | | | | | | | | | | | | | | Now that DRAM initialization and clock setup is supported, we can enable SPL for the A80. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add initial clock setup for sun9i for SPLPhilipp Tomsich2016-10-30-5/+223
| | | | | | | | | | | | | | | | | | | | This is a cleaned up version set_pll() from Allwinner's boot0 source (bootloader/basic_loader/bsp/bsp_for_a80/common/common.c). [wens@csie.org: Added commit message; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable SMP mode for the boot CPU on sun9i (A80)Philipp Tomsich2016-10-30-1/+2
| | | | | | | | | | | | | | | | | | | | Since the A80 has many cores which we intend to use in SMP fashion, we should set the SMP bit for the boot CPU. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add gtbus-initialisation for sun9iPhilipp Tomsich2016-10-30-1/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: DRAM initialisation for sun9iPhilipp Tomsich2016-10-30-15/+1273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-30-22/+67
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| * tools: add mksunxiboot to tools-all targetStefan Brüns2016-10-30-1/+2
| | | | | | | | | | | | | | mksunxiboot is useful outside of u-boot, it is e.g. used by sunxi-tools. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: A64: enable USB supportAmit Singh Tomar2016-10-30-6/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Update DRAM clock for Olimex A20 boardsStefan Mavrodiev2016-10-30-1/+1
| | | | | | | | | | | | | | | | | | Originally dram clock was set to 480MHz, but this behaves unstable. To improve stability the clock is reduced to 384MHz Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dts: Pine64: add Ethernet aliasAndre Przywara2016-10-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | The sun8i-emac driver works fine with the A64 Ethernet IP, but we are missing an alias entry to trigger the driver instantiation by U-Boot. Add the line to point U-Boot to the Ethernet DT node. This enables TFTP boot on the Pine64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT definesMasahiro Yamada2016-10-30-5/+0
| | | | | | | | | | | | | | | | | | ARCH_SUNXI selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT is not used. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXIJagan Teki2016-10-30-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SUNXI -> CONFIG_ARCH_SUNXI and removed CONFIG_SUNIX from config_whitelist.txt Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-10-29-2/+45
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| * | dm: mmc: socfpga: fix MMC_OPS supportSylvain Lesne2016-10-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at runtime. This adds the missing fields in the driver declaration. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-27-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-10-29-33/+21
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| * | | drivers: USB: OHCI: allow compilation for 64-bit targetsAndre Przywara2016-10-29-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OHCI has a known limitation of allowing only 32-bit DMA buffer addresses, so we have a lot of u32 variables around, which are assigned to pointers and vice versa. This obviously creates issues with 64-bit systems, so the compiler complains here and there. To allow compilation for 64-bit boards which use only memory below 4GB anyway (and to avoid more invasive fixes), adjust some casts and types and assume that the EDs and TDs are all located in the lower 4GB. This fixes compilation of the OHCI driver for the Pine64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
| * | | usb: xhci-mvebu: use xhci_deregister() for .remove callbackMasahiro Yamada2016-10-27-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | No need to use a wrapper that is equivalent to xhci_deregister(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | usb: ehci-vf: use ehci_deregister() for .remove callbackMasahiro Yamada2016-10-27-12/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | This driver was recently converted to Driver Model, so missed the subsystem-wide cleanups by commit 405273427366 ("usb: replace ehci_*_remove() with usb_deregister()"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-10-29-432/+879
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| * | ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada2016-10-29-23/+391
| | | | | | | | | | | | | | | | | | Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada2016-10-29-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada2016-10-29-44/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada2016-10-29-294/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3Masahiro Yamada2016-10-29-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The USB boot without the stand-by MPU is available on ES3 or later of LD11 SoC, but the code in this if-conditional block must not be run when booting from USB. Check if the boot device is USB, and skip the code in the case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabledMasahiro Yamada2016-10-29-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8Masahiro Yamada2016-10-29-3/+3
| | | | | | | | | | | | | | | | | | The status register should be polled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.hMasahiro Yamada2016-10-29-4/+4
| | | | | | | | | | | | | | | | | | | | | This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: update DRAM init code for LD20 SoC (3rd)Masahiro Yamada2016-10-29-36/+83
| | | | | | | | | | | | | | | | | | | | | | | | - Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove unused board attribute macrosMasahiro Yamada2016-10-29-3/+0
| | | | | | | | | | | | | | | | | | After SoC evaluation, they turned out unnecessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: enable SSC for more PLLs for LD20 SoCMasahiro Yamada2016-10-29-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove unneeded mdelay() in PLL setting functionMasahiro Yamada2016-10-29-2/+0
| | | | | | | | | | | | | | | | | | This delay is already cared by the callers of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: adjust fdt_file environment handling to latest LinuxMasahiro Yamada2016-10-29-12/+9
| | | | | | | | | | | | | | | | | | | | | The environment fdt_file is useful to remember the appropriate DTB file name. Adjust it to the recent renaming in the upstream kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | configs/chromebox_panther_defconfig: Re-enable CONFIG_DM_PCITom Rini2016-10-29-0/+1
| | | | | | | | | | | | | | | | | | This was turned off by accident, re-enble. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | MAINTAINERS: Update Jagan's emailJagan Teki2016-10-29-2/+2
| | | | | | | | | | | | Signed-off-by: Jagan Teki <jagan@openedev.com>
* | | travis-ci: build Tegra boardsStephen Warren2016-10-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7 Tegra boards aren't currently covered by any other travis-ci jobs. Add a new job to build them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | travis-ci: compile with buildman when running test/pyStephen Warren2016-10-29-27/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use buildman to compile any U-Boot binary tested by test/py. This re-uses all the work done elsewhere to make buildman work within Travis-CI, in particular related to toolchain downloading and buildman config file creation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | travis-ci: don't invoke exit on successStephen Warren2016-10-28-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Invoking exit prevents any subsequent build commands from running, and future patches will add extra commands. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | travis-ci: use buildman -P everywhereStephen Warren2016-10-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This places build results into a board-specific directory rather than a buildman-thread-specific directory. This is required so that we can access the directory from test.py, and there's no risk of a particular build's results being over-written by another build performed by the same thread. In theory, this can lead to slower builds when building many different boards in a single buildman thread, since it removes the possibility of incremental builds between boards. In practice however I didn't notice longer build times when when enabling this option; if anything build times decreased although I suspect that's simply due to general variations in build performance across different machines within the Travis CI infra-structure. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | travis-ci: centralize ~/.buildman editingStephen Warren2016-10-28-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any time an x86 toolchain is used, we need to edit ~/.buildman to reference it. Move the editing logic into a central place so that it doesn't have to be duplicated everywhere that uses the x86 toolchain; future patches will add additional cases where it's used. It would be nice if we could unconditionally write all of ~/.buildman at once. Unfortunately, buildman fails if any toolchain mentioned in a toolchain-prefix entry doesn't exist, even if it doesn't need to use it for the current build. The sandbox/x86 build definition currently does nothing more than edit ~/.buildman; no builds are run. Fix this by not defining a custom script for this build, and hence preventing that stanza from replacing the default script. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | travis-ci: use correct exit code on errorsStephen Warren2016-10-28-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phrase "if [ $? -ne 0 ]; then exit $?; fi" doesn't work correctly; by the time the "exit" statement runs, $? has already been over-written by the result of the [ command. Fix this by explicitly storing $? and then using that stored value in both the test and the error-case exit statement. This change also converts from textual comparison to integer comparison, since the exit code is an integer and there's no need to convert it to a string for comparison. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | travis-ci: Use = not : when writing ~/.buildmanStephen Warren2016-10-28-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Travis CI seems to be confused when there's a colon in an echo command, and this is currently worked around using a variable that contains the text we want to echo. Use = syntax instead so that we can remove the work-around; it's rather confusing until you find out what it's for. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
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