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* MLK-11304 MX6 SabreSD: Disable HDMI detectPeng Fan2016-03-25-1/+1
| | | | | | | | | | | | | | | | As the HDMI splash screen feature is not well supported, we should not set it to be the default display. In case, users leave the 'panel' uboot environment variable empty and connect the board with a HDMI monitor, the HDMI detect funtion will work and enable the HDMI splash screen. So, this patch disables HDMI detect function so that users may only explicitly set the 'panel' variable to be 'HDMI' to use HDMI splash screen. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit d482c54a9fbf458fdb2270cf990d8ec727823bb1)
* MLK-10747-2 video: ipu: Enable/disable LDB_DI clock when necessaryLiu Ying2016-03-25-8/+67
| | | | | | | | This patch adds enable/disable hooks support for ldb_di[0/1] clocks and enables/disables them when necessary. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 615d4c51679a6c2ee0ed4c5e3922eec76646eef1)
* MLK-10747-1 video: ipu: Build ldb_di clock relevant code only for MX6 and MX53Liu Ying2016-03-25-1/+13
| | | | | | | | The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock relevant code be built only for them. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 3e40c7466ae7d1d6ca74011bfe69ae059d412a3b)
* MLK-10774-2 HDMI: splash screen function enhancementPeng Fan2016-03-25-34/+79
| | | | | | | | | | | | | | | -Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5028519b434d5dfbe53c48ac4b115ff8b69bbac7)
* MLK-12214 NAND:apbh_dma: Fix logically dead code issueYe.Li2016-03-25-3/+3
| | | | | | | | | | The list_first_entry always assumes the list is not empty, it won't return NULL pointer when the list is empty. So the "if (pdesc == NULL)" becomes a dead code. Fix the issue by calling the list_empty before the list_first_entry. (Coverity CID 29934) Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-11718-2: mtd: nand: change the BCH layout setting for large oob NANDHan Xu2016-03-25-38/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | The cod change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes). Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11718-1: mtd: nand: change the maximum nange page size and oob sizeHan Xu2016-03-25-1/+3
| | | | | | | enlarge the maximum nand page size and oob size to 16k byte and 1280byte. Signed-off-by: Han Xu <b45815@freescale.com>
* ENGR00315894-60 GPIO: Modify driver mxc_gpio to support RDC SemaphoresYe.Li2016-03-25-0/+53
| | | | | | | | | | | | | | | | | | | | | For GPIO group which shared by multiple masters, it may set in RDC to shared and semaphore required. Before access the GPIO register, the GPIO driver must get the RDC semaphore, and release the semaphore after the GPIO register access. When CONFIG_MXC_RDC is set, the features related to RDC semaphores is enabled in mxc_gpio driver. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 84d63e2e2ce12f714e88baad8b2325684614a7c1) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: drivers/gpio/mxc_gpio.c (cherry picked from commit c9943b9c8a78bb2c9886bfe582e82978387d8dee) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit faf94726cac8316c4342e19936f1e03ef283ace3)
* MLK-11528 imx: mx6ul check fuse before init beePeng Fan2016-03-25-1/+11
| | | | | | | | | | | | Need to check fuse bit 25 of bank 0 word 4 before initialize bee. The bit: 0 means bee enabled, 1 means bee disabled. If disabled, continuing initialize bee will cause system hang, so need to check this bit before initialize bee. Add macro to enable BEE in header file, default disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ef4cb7c53418e4e1dd7cfcb7c6974cfea77ef3c0)
* MLK-10958 imx: mx6ul support Bus Encryption EnginePeng Fan2016-03-25-1/+507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL. Supported feature: 1. SNVS key and soft key 2. CTR and ECB mode 3. Specify address region to bee. Two commands are included: bee init [key] [mode] [start] [end] - BEE block initial "Example: bee init 1 1 0x80000000 0x80010000\n" bee test [region] "Example: bee test 1\n" Mapping: [0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)] [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)] Whatever start is, start - (start + size -1) will be fixed mapping to 0x10000000 - (0x10000000 + size - 1) Since default AES region's protected size is SZ_512M, so on mx6ul evk board, you can not simply run 'bee init', it will overlap with uboot execution environment, you can use 'bee init 0 0 0x80000000 0x81000000'. If want to use bee, Need to define CONFIG_CMD_BEE in board configuration header file, since CONFIG_CMD_BEE default is not enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 29b9bdbbdac9678dba9b7bc2d3662598e9c548a5)
* MLK-12416-5: spi: qspi: align to 2015.04Peng Fan2016-03-25-936/+693
| | | | | | | | | | Switch to use 2015.04 qspi driver. Change header file to adapt to the driver. To i.mx6sx, move config to header file. Tested read/write/erase on 6ulevk/sxai/sxsdb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12416-4: imx: mx6: update imx-regs.hPeng Fan2016-03-25-8/+123
| | | | | | Update imx-regs.h to align with 2015.04 Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12416-3: imx: mx6ul evk: support NANDPeng Fan2016-03-25-1/+83
| | | | | | | Add NAND pinmux settings and related macros. Default not enabled, need hardware rework. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12416-2: imx: mx6ul evk: Add PHYS_SDRAM_SIZE and CMA macroPeng Fan2016-03-25-0/+10
| | | | | | | | define PHYS_SDRAM_SIZE future usage. define CMA for kernel usage, default is 320MB, but we do not have enough memory on 9x9 evk lpddr2 board, so swith to 96MB. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12416-1: imx: mx6ul evk: switch to non SPLPeng Fan2016-03-25-8/+316
| | | | | | Switch to default not support SPL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-10931 imx: wdog: Turn off internal reset signal for mx7dYe.Li2016-03-25-1/+5
| | | | | | | Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB for mx7d. So that the warm reset is disabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12417 fsl_esdhc: Update clock enable bits for USDHCYe Li2016-03-25-2/+7
| | | | | | | | | | | | | | | | The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The community driver uses RSTA to replace the clock gate off operation. But this is not a good solution. This is because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the codes. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12102 mmc: fsl: introduce wp_enablePeng Fan2016-03-25-3/+7
| | | | | | | | | | | | | | | | | | Introudce wp_enable. If want to check WPSPL, then in board code, need to set wp_enable to 1. Take i.MX6UL for example, to some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. Suggested-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 327dad065f6f9a2b29bd646efc7a08a4c01a4ad3)
* MLK-12001 MMC:USDHC: Clear DLL_CTRL delay line settings at driver initYe.Li2016-03-25-0/+3
| | | | | | | | | | | | | Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. U-boot should re-init the USDHC not reply on the value set by boot from. On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021, when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors. Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f355f117a6d735b0c3cba79f1cb24829cf8cae25)
* ENGR00315499-19 Fix eMMC fast boot hang issueYe.Li2016-03-25-11/+36
| | | | | | | | | | | | | | | When booting in eMMC fast boot, the uboot v2013.04 always hangs. The root cause is that MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Signed-off-by: Ye Li <b37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit cf77f982b9969eda4cb5af2a78d3d40e17290756)
* MLK-11035 imx: mx6 update thermal slope factorsPeng Fan2016-03-25-2/+2
| | | | | | | | | | | | | | | | | | | | | From temp sensor guys: " I confirmed the math with him(had do the accuracy study) today. The new, final equation is: Tmeas = (Nmeas - n1) / slope + t1 + offset n1= fused room count t1= 25 offset=3.580661 slope= 0.4148468 – 0.0015423*n1 " 87723f903454aaf17336e0fe9098ea7911c19f3c update the thermal with not accurate slope parameters. This patch fix it. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 0d4904f5929cecd66f0b60cf8ebdcb0e6a2f733e)
* MLK-10827 imx: mx6 update thermal driver according new equationPeng Fan2016-03-25-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC guys: " After a thorough accuracy study of the Temp sense circuit, we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. Old Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) Where Troom,cal = 25C and Slope = 0.4297157 – (0.0015974 * Count room fuse) New Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset Where Troom,cal = 25C and Slope = 0.4445388 – (0.0016549 * Count room fuse) Offset = 3.580661 " According the new equation, update the thermal driver. c1 and c2 changed to u64 type and update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 87723f903454aaf17336e0fe9098ea7911c19f3c)
* Prepare v2016.03Tom Rini2016-03-14-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* mx6slevk: Fix the power up of the Ethernet PHYFabio Estevam2016-03-13-5/+4
| | | | | | | | | GPIO4_21 is the LAN8720 power pin, not the LAN8720 reset pin. Fix that, so that we can have Ethernet functional again. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* sf: Correct data types in stm_is_locked_sr()Marek Vasut2016-03-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The stm_is_locked_sr() function is picked from Linux kernel. For reason unknown, the 64bit data types used by the function and present in Linux were replaced with 32bit unsigned ones, which causes trouble. The testcase performed was done using ST M25P80 chip. The command used was: => sf protect unlock 0 0x10000 The call chain starts in stm_unlock(), which calls stm_is_locked_sr() with negative ofs argument. This works fine in Linux, where the "ofs" is loff_t, which is signed long long, while this fails in U-Boot, where "ofs" is u32 (unsigned int). Because of this signedness problem, the expression past the return statement to be incorrectly evaluated to 1, which in turn propagates back to stm_unlock() and results in -EINVAL. The correction is very simple, just use the correctly sized data types with correct signedness in the function to make it work as intended. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dm: ti_qspi: Fix conversion of address to a pointerLokesh Vutla2016-03-12-3/+7
| | | | | | | | | | | | | | TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address instead of a pointer for the uart base") Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* exynos5: common: Enable CONFIG_USB_ETHER_RTL8152 ethernet supportAnand Moon2016-03-11-0/+1
| | | | | | | | | | | | Enable CONFIG_USB_ETHER_RTL8152 support for Odroid XU4 which has support for RTL8153-CG gigabit Ethernet adapter, connected over USB 3.0. commit 9dc8ba19c50fc0b1623c654bcfe6caa903a4c36c added support for Realtek 8152/8153 driver. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-03-10-9/+9
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| * rockchip: rk3288: correct sdram settingChris Zhong2016-03-10-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2, and it expects uboot to store the value using a same protocol. But now the ddr setting value is different with DMC, so if you enable the DMC, system would crash in kernel. Correct the sdram setting here, according to the requirements of kernel. [0] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c Signed-off-by: Chris Zhong <zyw@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: make configure_emmc() empty for Firefly-RK3288FUKAUMI Naoki2016-03-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for Firefly-RK3288. (it's fine for Rock2) $ gcc --version gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204 Copyright (C) 2015 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin u-boot-spl-dtb.img Warning: SPL image is too large (size 0x80d0) and will not boot to reduce size of SPL image, this patch makes configure_emmc() empty for Firefly-RK3288 as same as Rock2. Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-By: Vagrant Cascadian <vagrant@debian.org>
| * rockchip: rk3036: change ddr frequency to 400MLin Huang2016-03-10-1/+1
| | | | | | | | | | | | | | | | | | emac may use dpll as clock parent, and it request the clock frequency multiples of 50, so change ddr frequency to 400M. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=yDaniel Schwierzeck2016-03-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work with EB-only toolchains like the one from kernel.org. If one do not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with: /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): compiled for a big endian system and target is little endian /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): endianness incompatible with that of the selected emulation /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o) /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): compiled for a big endian system and target is little endian /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): endianness incompatible with that of the selected emulation /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o) /work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed One example for a failing build is Travis CI. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | MIPS: fix mips_cache fallback without __builtin_mips_cacheMatthias Schiffer2016-03-09-1/+1
|/ | | | | | | | | | | The "R" constraint supplies the address of an variable in a register. Use "r" instead and adjust asm to supply the content of addr in a register instead. Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations") Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* malloc: remove !gd handlingStephen Warren2016-03-08-1/+1
| | | | | | | | | | | | | Following the previous patch, malloc() is never called before gd is set, so we can remove the special-case check for this condition. This reverts commit 854d2b9753e4 "dlmalloc: ensure gd is set for early alloc". Cc: Rabin Vincent <rabin@rab.in> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* malloc: use hidden visibilityStephen Warren2016-03-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running sandbox, the following phases occur, each with different malloc implementations or behaviors: 1) Dynamic linker execution, using the dynamic linker's own malloc() implementation. This is fully functional. 2) After U-Boot's malloc symbol has been hooked into the GOT, but before any U-Boot code has run. This phase is entirely non-functional, since U-Boot's gd symbol is NULL and U-Boot's initf_malloc() and mem_malloc_init() have not been called. At least on Ubuntu Xenial, the dynamic linker does make both malloc() and free() calls during this phase. Currently these free() calls crash since they dereference gd, which is NULL. U-Boot itself makes no use of malloc() during this phase. 3) U-Boot execution after gd is set and initf_malloc() has been called. This is fully functional, albeit via a very simple malloc() implementation. 4) U-Boot execution after mem_malloc_init() has been called. This is fully functional with a complete malloc() implementation. Furthermore, if code that called malloc() during phase 1 calls free() in phase 3 or later, it is likely that heap corruption will occur, since U-Boot's malloc implementation will assume the pointer is part of its own heap, although it isn't. I have not actively observed this happening. To prevent phase 2 from happening, this patch makes all of U-Boot's malloc library public symbols have hidden visibility. This prevents them from being hooked into the GOT, so only code in the U-Boot binary itself actually calls them; any other code will call into the standard C library malloc(). This also avoids the "furthermore" issue mentioned above. I have seen references to this GCC pragma in blog posts from 2008, and RHEL5's ancient gcc appears to accept it fine, so I believe it's quite safe to use it without checking gcc version. Cc: Rabin Vincent <rabin@rab.in> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sandbox: Fix building with LLVMTom Rini2016-03-08-1/+7
| | | | | | | | | | | | - The macro __BIGGEST_ALIGNMENT__ is gcc-specific. If it is not defined we'll just assume 16. This is correct for at least the common cases and LLVM does not provide an equivalent macro. - When linking U-Boot we're passing -T to the linker, and while gcc will just pass this along with LLVM we need to be specific. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* omap3: Use raw SPL by default for mmc1Alexander Graf2016-03-08-2/+0
| | | | | | | | | | | Now that we fall back to the FS code path when we don't find u-boot at the raw sector offset, there is no good reason to not default to raw boot. With this patch, I can successfully boot u-boot from a raw sector offset on beagle-xm. Signed-off-by: Alexander Graf <agraf@suse.de>
* api: Export API structure address as an environment variableStanislav Galabov2016-03-08-0/+1
| | | | | | | | | | This patch makes the U-Boot api export its structure address as an environment variable, so it can be used to directly hint FreeBSD's loader of api's location. The relevant FreeBSD loader change is currently under review at: https://reviews.freebsd.org/D5492 Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>
* OMAP3: am3517_evm: Add NAND MTD partitions with UBI/UBIFS supportDerald D. Woods2016-03-08-158/+153
| | | | | | | | | | | | - Add required UBI/UBIFS config definitions - Add reasonable MTD partition layout - Remove JFFS2 config definitions - Drop some CFI verbage and definitions - Make comment 'one-liners' truly one line - Improve readability and content arrangement Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* OMAP3: am3517_evm: Use BCH8 ECC for NANDDerald D. Woods2016-03-08-7/+16
| | | | | | | | Select 8-bit BCH ecc-scheme with s/w based error correction - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: allow debug_ll_init() to do nothing for unknown SoCsMasahiro Yamada2016-03-09-0/+1
| | | | | | | This function should just return for unknown SoCs rather than writing unexpected values to registers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIERMasahiro Yamada2016-03-09-9/+9
| | | | | | | | | | CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: set input-enable before pin-muxingMasahiro Yamada2016-03-09-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. [ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ] Fixes: 5dc626f83619 ("pinctrl: uniphier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix build error when CONFIG_CMD_DDRMPHY_DUMP=yMasahiro Yamada2016-03-09-16/+2
| | | | | | | | The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data"). Fixes: 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: document how-to-build for Ace and Sanji boardsMasahiro Yamada2016-03-09-0/+8
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-03-04-2/+12
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| * usb: dwc2: disable erroneous overcurrent conditionDinh Nguyen2016-03-05-1/+5
| | | | | | | | | | | | | | | | | | | | | | For the case where an external VBUS is used, we should enable the external VBUS comparator in the driver. This would prevent an unnecessary overcurrent error which would then disable the host port. The overcurrent condition was happening on the SoCFPGA Cyclone5 devkit, thus USB was not working on the devkit. This patch fixes that problem. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * usb: gadget: composite: Correct recovery path for registerSam Protsenko2016-03-01-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case when usb_composite_register() failed once (for whatever reason), it will fail further even if all conditions are correct. Example: => fastboot 2 Invalid Controller Index couldn't find an available UDC g_dnl_register: failed!, error: -19 exit not allowed from main input shell. => fastboot 0 g_dnl_register: failed!, error: -22 exit not allowed from main input shell. Despite that 0 is correct index for USB controller, "fastboot 0" command will fail, because "composite" structure wasn't cleared properly on previous fail (on "fastboot 2" command). This patch fixes that erroneous behavior, allowing us to use composite even after previous failure. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
* | board: tbs2910: Fix eMMC BOOTCFG valueSoeren Moch2016-03-02-1/+1
| | | | | | | | | | | | | | | | | | Fix the BOOTCFG value for eMMC in the same way as commit 214c3f0f9921250eb336c7effadcc16158ea9df5 [imx: MX6DQ{P}/DL:SABRESD Fix bmode eMMC failure] did for sabresd. Signed-off-by: Soeren Moch <smoch@web.de>
* | mx53ard: Move to booting zImageFabio Estevam2016-03-02-8/+10
| | | | | | | | | | | | | | | | | | | | Move to booting a zImage kernel by default to align with the other i.MX boards. While at it, adjust the fdt_addr so that we can boot a standard mainline kernel. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
generated by cgit v1.1 at 2024-12-25 16:44:19 +0000