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* arm: mx6: cm-fx6: setup hdmi only on hdmi enableNikita Kiryanov2015-08-02-6/+3
| | | | | | | | | Refactor display code to only setup hdmi if do_enable_hdmi() is invoked. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: add support for displaytype env varNikita Kiryanov2015-08-02-1/+4
| | | | | | | | | | | | | Add support for selecting display preset using the environment variable "displaytype". This is a preparation for future merging of compulab omap3_display.c display selection code with the cm-fx6 display selection code. The "panel" environment variable is retained for backwards compatibility. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: make it possible to not init displayNikita Kiryanov2015-08-02-25/+48
| | | | | | | | | | | | | | | | | Implement a cm-fx6 specific board_video_skip() to provide the option to not initialize the display. The new function does not init display if the environment variable "panel" is not defined, or if it is set to an unsupported value. Collateral changes: - Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific). - Don't use detect_hdmi(), since env controlled init makes it unnecessary. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: map HDMI to IPU1 DI0 explicitlyNikita Kiryanov2015-08-02-0/+2
| | | | | | | | | | | | | | | U-Boot does not explicitly assign the display to an IPU interface. Instead, it relies on the power-on default of DI0. Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI display no longer works in U-Boot. Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board supportPeng Fan2015-08-02-7/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800) CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: mx6sabresd/sabreauto runtime setting fdt_filePeng Fan2015-08-02-12/+38
| | | | | | | | | | | | | Detect the SOC and board variant at runtime and change the dtb name, but not hardcoding the fdt_file env variable. Take the following patch as a reference. Íd58699b157df75f1aa0b363ea9c21add21a0c "mx6cuboxi: Load the correct 'fdtfile' variable" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6qp Enable PRG clock for IPUPeng Fan2015-08-02-0/+5
| | | | | | | | | | The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-08-02-1/+2
| | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-02-34/+49
| | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-02-5/+16
| | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* cgtqmx6eval: Use standard boot scriptOtavio Salvador2015-07-26-28/+66
| | | | | | | Use more standard boot scripts and also add the capability of booting via NFS. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Align DCD settings with Congatec's U-bootOtavio Salvador2015-07-26-77/+51
| | | | | | | Use the same DCD settings from Congatec's U-boot tree for the P/N 016113 card. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add SATA supportOtavio Salvador2015-07-26-0/+14
| | | | | | Add SATA support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add splash screen supportOtavio Salvador2015-07-26-0/+193
| | | | | | Add LVDS and HDMI support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add USB supportOtavio Salvador2015-07-26-0/+59
| | | | | | Add USB support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add PMIC supportOtavio Salvador2015-07-26-0/+98
| | | | | | | | cgtqmx6eval has a PFUZE100 FSL PMIC connected to I2C2. Add support for it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add thermal supportOtavio Salvador2015-07-26-0/+11
| | | | | | | | Add thermal support so that we can see the following message on boot: CPU: Industrial temperature grade (-40C to 105C) at 33C Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add ESDHC3 supportOtavio Salvador2015-07-26-1/+21
| | | | | | | | cgtqmx6eval has an eMMC connected to ESDHC3. Add support for it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Fit into single linesOtavio Salvador2015-07-26-4/+2
| | | | | | There is no need to use multiple lines when they fit into a single line. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Improve the error handlingOtavio Salvador2015-07-26-3/+7
| | | | | | | | Perfoming an OR operation on the error is not a good approach. Return the error immediately for each ESDHC instance instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Staticize when possibleOtavio Salvador2015-07-26-4/+4
| | | | | | Declare 'static' when possible. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Use the default CONFIG_SYS_PBSIZEOtavio Salvador2015-07-26-3/+0
| | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Use default promptOtavio Salvador2015-07-26-3/+0
| | | | | | Remove the custom prompt and use the default instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mmc:fsl_esdhc invalidate dcache before readPeng Fan2015-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* mx6sxsabresd: Use 'int' for return valuesFabio Estevam2015-07-26-1/+2
| | | | | | | | | | The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should be of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sabresd: Use 'int' for return valuesFabio Estevam2015-07-26-1/+2
| | | | | | | | | | The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* warp: Add MAX77696 supportFabio Estevam2015-07-26-0/+61
| | | | | | | | Warp has a MAX77696 PMIC connected via I2C1 bus. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* power: pmic: Add support for MAX77696 PMICFabio Estevam2015-07-26-0/+93
| | | | | | Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* thermal: Fix commentsFabio Estevam2015-07-26-12/+4
| | | | | | | | | | It seems that many comments were copied from the I2C uclass, so adjust the comments for the thermal class. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Simon Glass <sjg@chromium.org>
* imx: imximage: add new CHECK/CLR BIT commandAdrian Alonso2015-07-26-27/+93
| | | | | | | | | | | | | | | * Extend imximage DCD version 2 to support DCD commands CMD_WRITE_CLR_BIT 4 [address] [mask bit] means: while ((*address & ~mask) != 0); CMD_CHECK_BITS_SET 4 [address] [mask bit] means: while ((*address & mask) != mask); CMD_CHECK_BITS_CLR 4 [address] [mask bit] means: *address = *address & ~mask; * Add set_dcd_param_v2 helper function to set DCD command parameters Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoMStefan Roese2015-07-26-0/+437
| | | | | | | | | This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-1771/+2544
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| * Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-15-1623/+2072
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| | * pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * pci: Configure expansion ROM during auto config processBin Meng2015-07-14-40/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * drivers: block: Remove the ata_piix driverBin Meng2015-07-14-789/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Adjust config option order in defconfig for Crown Bay and MinnowmaxBin Meng2015-07-14-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig' result so that the config option order matches Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * tools: ifdtool: Write correct offset on 32-bit machineBin Meng2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff, which is wrong for u-boot.rom components like u-boot-x86-16bit.bin. Change to use strtoll() so that it works on both 32-bit and 64-bit machines. Reported-by: Fei Wang <wangfei.jimei@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add binary blob checksums for Minnowboard MAXSimon Glass2015-07-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To try to reduce the pain of confusion of binary blobs, add MD5 checksums for the current versions. This may worsen the situation as new versions appear, but it should still be possible to obtain these versions, and thus get a working setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: x86: minnowmax: Move PCI to use driver modelSimon Glass2015-07-14-47/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-14-27/+8
| | | | | | | | | | | | | | | | | | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add ROM image description for minnowmaxSimon Glass2015-07-14-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | The layout of the ROM is a bit hard to discover by reading the code. Add a table to make it easier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: spi: Enable environment for minnowmaxSimon Glass2015-07-14-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable a SPI environment and store it in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * dm: spi: Correct BIOS protection logic for ICH9Simon Glass2015-07-14-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
| | * dm: spi: Correct status register access widthSimon Glass2015-07-14-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| | * x86: crownbay: Enable graphics supportBin Meng2015-07-14-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Remove MARK_GRAPHICS_MEM_WRCOMBBin Meng2015-07-14-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-09-19 21:04:34 +0000