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* net: stm32: add designware mac glue code for stm32Michael Kurz2017-01-28-3/+122
| | | | | | | | This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* ARM: stm32: use clock setup function defined in clock.cMichael Kurz2017-01-28-30/+15
| | | | | | | | | | | Use the clock setup function defined in clock.c instead of setting the clock bits directly in the drivers. Remove register definitions of RCC in rcc.h as these are already defined in the struct in stm32.h Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: stm32: fix stm32f7 sdram fmc base addressMichael Kurz2017-01-28-3/+2
| | | | | | | | | The fmc base address is defined twice, once in fmc.h and once in stm32.h. Fix wrong definition in stm32.h. Remove the definiton in fmc.h. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: stm32: cleanup stm32f7 filesMichael Kurz2017-01-28-124/+111
| | | | | | | | | | | | Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - use rcc struct instead of macro additions Add missing stm32f7 register in rcc struct Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA<vikas.manocha@st.com>
* ARM: DTS: stm32: add stm32f746-disco device tree filesMichael Kurz2017-01-28-0/+242
| | | | | | | | | | | This patch adds the DTS source files needed for stm32f746-disco board The files are based on the stm32f429/469 files from current linux kernel. Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi" Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* ARM: DTS: stm32: add stm32f746 device tree pin control filesMichael Kurz2017-01-28-0/+1324
| | | | | | | | | This patch adds pin control definitions for use in device tree files The definitions are based on the stm32f746 files from current linux kernel "include/dt-bindings/pinctrl/stm32f746-pinfunc.h". Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703Adam Ford2017-01-28-2/+48
| | | | | | | | | | | | The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but anything else is lumped into 36XX/37XX with an assumed 1GHz speed. Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ). This also adds the ability to distinguish between the DM3730, DM3725, AM3715, and AM3703 and correctly display their maximum speed. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
* arm: omap3: Fix cpuinfo frequency spellingLadislav Michl2017-01-28-3/+3
| | | | | | Frequency is measured in Hz. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* Revert "armv8: release slave cores from CPU_RELEASE_ADDR"Masahiro Yamada2017-01-28-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8c36e99f211104fd7dcbf0669a35a47ce5e154f5. There is misunderstanding in commit 8c36e99f2111 ("armv8: release slave cores from CPU_RELEASE_ADDR"). How to bring the slave cores into U-Boot proper is platform-specific. So, it should be cared in SoC/board files instead of common/spl/spl.c. As you see SPL is the acronym of Secondary Program Loader, there is generally something that runs before SPL (the First one is usually Boot ROM). How to wake up slave cores from the Boot ROM is really SoC specific. So, the intention for the spin table support is to bring the slave cores into U-Boot proper in an SoC specific manner. (this must be done after relocation. see below.) If you bring the slaves into SPL, it is SoC own code responsibility to transfer them to U-Boot proper. The Spin Table defines the interface between a boot-loader and Linux kernel. It is unrelated to the interface between SPL and U-Boot proper. One more thing is missing in the commit; spl_image->entry_point points to the entry address of U-Boot *before* relocation. U-Boot relocates itself between board_init_f() and board_init_r(). This means the master CPU sees the different copy of the spin code than the slave CPUs enter. The spin_table_update_dt() protects the code *after* relocation. As a result, the slave CPUs spin in unprotected code, which leads to unstable behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: spin-table: add more information in Kconfig helpMasahiro Yamada2017-01-28-2/+4
| | | | | | | | | | | | | | | | | | | | | This feature seems to be sometimes misunderstood. The intention is: [1] Bring the slaves into the U-Boot proper image, not SPL (unless you have a special reason to do otherwise). [2] The operation must be done in a board (SoC) specific manner since how to wake the slaves from the Boot ROM is SoC specific. [3] The slaves must enter U-Boot proper after U-Boot relocates itself because the "cpu-release-addr" property points to the relocated memory area. [2] is already explained in the help. We can make [1] even clearer by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing, so I am adding it to the list. Instead, "before the master CPU jumps to the kernel" is a matter of course, so removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* board/chiliboard: Add support for chiliBoardMarcin Niestroj2017-01-28-0/+532
| | | | | | | | | | | | | chiliBoard is a development board which uses chiliSOM as its base. Hardware specification: * chiliSOM (TI AM335x, DRAM, NAND) * Ethernet PHY (id 0) * USB host (usb1) * MicroSD slot (mmc0) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: am335x: Add support for chiliSOMMarcin Niestroj2017-01-28-0/+206
| | | | | | | | | | | | | | | | | chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * TI AM335x processor * 128M, 256M or 512M DDR3 memory * up to 256M NAND We place source inside arch/arm/mach-omap2/ directory and make it possible to reuse initialization code (i.e. DDR, NAND init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: Add a config for AM335x High Security EVMAndrew F. Davis2017-01-28-0/+63
| | | | | | | | | | | | | | | | | | Add a new defconfig file for the AM335x High Security EVM. This config is specific for the case of memory device booting. Memory device booting is handled separatly from peripheral booting on HS devices as the load address changes. This defconfig is the same as for the non-secure part, except for: CONFIG_TI_SECURE_DEVICE option set to 'y' CONFIG_ISW_ENTRY_ADDR updated for secure images. CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_USE_TINY_PRINTF option set to 'y' to reduce SPL size CONFIG_SPL_SYS_MALLOC_SIMPLE set to 'y' to reduce SPL size Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: Remove overwrite of relocated malloc limitAndrew F. Davis2017-01-28-1/+6
| | | | | | | | | | | spl_init on some boards is called after stack and heap relocation, on some platforms spl_relocate_stack_gd is called to handle setting the limit to its value CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN when simple SPL malloc is enabled during relocation. spl_init should then not re-assign the old pre-relocation limit when this is defined. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* malloc_simple: Add debug statements to memalign_simpleAndrew F. Davis2017-01-28-1/+5
| | | | | | | Add debug statements to memalign_simple to match malloc_simple. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* aspeed: Support for ast2500 Eval Boardmaxims@google.com2017-01-28-0/+94
| | | | | ast2500 Eval Board device tree and board specific configuration. Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Board init functions and common configs for ast2500 based boardsmaxims@google.com2017-01-28-1/+165
| | | | | | | | Add configuration file with parameters that are very likely to be shared by all ast2500-based boards. Add ast2500-board.c file with the init code that is very likely to be shared by all ast2500-based boards. Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+1273
| | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com2017-01-28-0/+420
| | | | | | | | | | | | | | | | | Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Note vendor-required status of certain MACH_TYPE valuesTom Rini2017-01-28-25/+12
| | | | | | | | | | | | | | In the cases of some boards, a MACH_TYPE number is used which is either not registered upstream or worse (for functionality) is re-using the number of a different (or reference) platform instead. Make sure we have a comment in these cases. Cc: Albert ARIBAUD <albert.aribaud@3adev.fr> Cc: Walter Schweizer <swwa@users.sourceforge.net> Cc: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de>
* am335x_shc: Drop MACH_TYPE usageTom Rini2017-01-28-19/+0
| | | | | | | | This board is using MACH_TYPE values that were clearly picked during development and not registered. Remove rather than support. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: Clean up MACH_TYPE_xxx usage after re-sync of mach-typesTom Rini2017-01-28-103/+12
| | | | | | | | With the latest mach-types values we have many instances where we no longer need to define a value and a few cases where the name (but not value) have changed slightly. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "arm: Remove unregister MACH_TYPE_xxx uses"Tom Rini2017-01-28-0/+52
| | | | | | | | | | This reverts commit 70b26cd057f42c7126088b49d4285955c8a00eae. This is not a strict revert as it is easier to fix board/atmark-techno/armadillo-800eva/armadillo-800eva.c to now the correct name (same value) than to revert that change too. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: Re-sync with full list of MACH_TYPE_xxx valuesTom Rini2017-01-28-1/+4064
| | | | | | | This re-syncs us with the official and full list of MACH_TYPE_xxx values from http://www.armlinux.org.uk/developer/machines/ Signed-off-by: Tom Rini <trini@konsulko.com>
* disk: convert CONFIG_PARTITION_TYPE_GUID to KconfigPatrick Delaunay2017-01-28-1/+8
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* cmd, disk: convert CONFIG_PARTITION_UUIDS, CMD_PART and CMD_GPTPatrick Delaunay2017-01-28-490/+500
| | | | | | | | | | | We convert CONFIG_PARTITION_UUIDS to Kconfig first. But in order to cleanly update all of the config files we must also update CMD_PART and CMD_GPT to also be in Kconfig in order to avoid complex logic elsewhere to update all of the config files. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* kbuild: add include linux/kconfig.h in config.hPatrick Delaunay2017-01-28-0/+1
| | | | | | | | Allow to use define CONFIG_IS_ENABLED in include/config_fallbacks.h Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* disk: convert CONFIG_EFI_PARTITION to KconfigPatrick Delaunay2017-01-28-68/+326
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* disk: convert CONFIG_AMIGA_PARTITION to KconfigPatrick Delaunay2017-01-28-4/+17
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* disk: convert CONFIG_ISO_PARTITION to KconfigPatrick Delaunay2017-01-28-59/+363
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* disk: convert CONFIG_DOS_PARTITION to KconfigPatrick Delaunay2017-01-28-430/+231
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* disk: convert CONFIG_MAC_PARTITION to KconfigPatrick Delaunay2017-01-28-55/+113
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* disk: convert CONFIG_PARTITIONS to KconfigPatrick Delaunay2017-01-28-2/+24
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-01-26-10/+624
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| * arm64: mvebu: Update bubt command MMC block device accessKonstantin Porotchkin2017-01-25-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the MMC block device access code in bubt command implementation according to the latest MMC driver changes. Change-Id: Ie852ceefa0b040ffe1362bdb7815fcea9b2d923b Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
| * arm64: mvebu: Enable SDHCI/MMC support for the db-88f7040/8040Stefan Roese2017-01-25-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the MMC support for the SDHCI controller on the Armada 7k db-88f7040 and the Armada 8k db-88f8040 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 7040-db: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada 7040-db dts file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 7k/8k: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada AP806 dtsi file which is used by the Armada 7k/8K SoCs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Enable SDHCI/MMC support for the db-88f3720Stefan Roese2017-01-25-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the MMC support for the SDHCI controller on the Armada 3700 db-88f3720 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 3720-db: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada 3700-db dts file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 3700: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada 3700 dtsi file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * mmc: Add Marvell Xenon SDHCI controller driverStefan Roese2017-01-25-0/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implementes platform specific code for the Xenon SDHCI controller which is integrated in the Marvell MVEBU Armada 37xx and Armada 7k / 8K SoCs. History: This driver is ported from the Marvell U-Boot version 2015.01 which is written by Victor Gu <xigu@marvell.com> with minor changes ported from the Linux driver which is written by Ziji Hu <huziji@marvell.com>. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: sdhci: Add support for optional controller specific set_ios_post()Stefan Roese2017-01-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SDHCI drivers might need to do some special controller configuration after the common clock set_ios() function has been called (speed / width configuration). This patch adds a call to the newly created function set_ios_port() when its configured in the host driver. This will be used by the Xenon SDHCI controller driver used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: sdhci: Clear SDHCI_CLOCK_CONTROL before configuring the new valueStefan Roese2017-01-25-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completely clears the SDHCI_CLOCK_CONTROL register before the new value is configured instead of just clearing the 2 bits SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some clock configurations will lead to the "Internal clock never stabilised." error message on the Xenon SDHCI controller used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. The Linux SDHCI core driver also writes 0 to this register before the new value is configured. So this patch simplifies the driver a bit and brings the U-Boot driver more in-line with the Linux one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | cmd: ubi: allow '-' to specify maximum volume sizeLadislav Michl2017-01-26-3/+5
| | | | | | | | | | | | | | | | | | Currently maximum volume size can be specified only if no other arguments are used. Use '-' placeholder as volume size to allow maximum volume size to be specified together with volume id and type. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-01-25-3/+37
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| * | powerpc: Enable flush and invalidate dcache by range for MPC85xxTony O'Brien2017-01-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f91a for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Cc: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun>
| * | mpc85xx: pcie: Implement workaround for Erratum A007815Tony O'Brien2017-01-24-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907Darwin Dingel2017-01-24-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz> Cc: York Sun <york.sun@nxp.com> [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* | | Drop CONFIG_CMD_DOCSimon Glass2017-01-25-30/+0
| | | | | | | | | | | | | | | | | | | | | This is not used in U-Boot, and the only usage calls a non-existent function. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-09-18 22:03:28 +0000