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* move: rockchip: move clock drivers into a subdirectoryHeiko Stübner2016-08-05-3/+10
| | | | | | | | | | | | With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
* rk3399: add basic soc driverKever Yang2016-08-05-0/+980
| | | | | | | | | | This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rockchip, sdram-channel 0xff fix remaining dtsSandy Patterson2016-08-05-2/+2
| | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add fastboot support for rk3036 boardXu Ziyuan2016-08-05-3/+112
| | | | | | | | Enable fastboot feature on rk3036, please refer to doc/README.rockchip for more detailed usage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* powerpc/86xx: Increase boot map size to 256 MiBScott Wood2016-08-03-10/+12
| | | | | | | | | | This is what Linux maps on classic PPC during boot, and modern kernel images don't fit within the current 8 MiB uncompressed limit. Adjust image load addresses to be above this limit to avoid conflicts. Signed-off-by: Scott Wood <oss@buserror.net> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-08-02-66/+82
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| * ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIPHou Zhiqiang2016-08-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | The PPA binary may be stored on QSPI flash instead of NOR. So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code by addition of a new QSPI specific flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT nodeHou Zhiqiang2016-08-02-0/+2
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Fixed the backward compatiblity issueHou Zhiqiang2016-08-02-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | Appended the compatible strings of old version PSCI to the latest version supported. And there are some psci functions' property must be added to DT only for psci version 0.1, including cpu_on, cpu_off, cpu_suspend, migrate. Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Removed unused codeHou Zhiqiang2016-08-02-17/+0
| | | | | | | | | | | | | | | | Identify the PSCI node only by its name, so removed the code finding it by compatible string. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Fix timing_cfg_2York Sun2016-08-02-1/+1
| | | | | | | | | | | | | | | | | | Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
| * board/freescale: Update MAINTAINERS filesYork Sun2016-08-02-9/+17
| | | | | | | | | | | | Update maintainers for secure boot targets. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043a: enable pxe commandsWenbin Song2016-08-02-0/+2
| | | | | | | | | | | | | | Enable pxe command for ls1043ardb and ls1043aqds. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012a: Update Refresh cycle for DDRPrabhakar Kushwaha2016-08-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | Refresh cycle value must be selected based on the frequency of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT] should be based on round up (tREFI/tCK) formula. For 500MHz, mdref value should be 0x0f3c8000. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012a: Enable DDR row-bank-column decodingPrabhakar Kushwaha2016-08-02-1/+1
| | | | | | | | | | | | | | | | | | | | Enable DDR row-bank-column decoding to decode DDR address as row-bank-column instead of bank-row-column for improving performance of serial data transfers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESETPrabhakar Kushwaha2016-08-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define inverse value QIXIS_LBMAP_MASK. Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD] as 0b11 i.e. PORESET during qixis_reset Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * crypto/fsl: Update blob cmd to accept 64bit addressesSumit Garg2016-08-02-4/+11
| | | | | | | | | | | | | | | | | | Update blob cmd to accept 64bit source, key modifier and destination addresses. Also correct output result print format for fsl specific implementation of blob cmd. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver: spi: fsl-qspi: remove compile WarningsYunhui Cui2016-08-02-1/+3
| | | | | | | | | | | | | | | | | | | | Warnins log: drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’: drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/mpc85xx: Update erratum workaround for A006379York Sun2016-08-02-1/+1
| | | | | | | | | | | | | | | | Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-08-02-59/+69
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| * | ARM64: zynqmp: Do not enable DM_MMC by defaultMichal Simek2016-08-02-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch: "dm: mmc: zynq: Convert zynq to use driver model for MMC" (sha1: 329a449f2c289b4de8f892fca1d9379ce5fd81b8) added dependency on enabling some MMC options by default. There are minimal ZynqMP configurations which require only minimal configurations to be enabled to keep u-boot size as lower as possible. Move options to defconfig instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Fix stack pointer initializationSoren Brinkmann2016-08-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This partly reverts commit: "ARM64: zynqmp: Add SPL support support" (sha1: e6a9ed04e78cf87ec97e306fa4e7a1669ef98df6) Stack can rewrite ATF code. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Define config USB_STORAGE through defconfigMichal Simek2016-08-02-1/+5
| | | | | | | | | | | | | | | | | | | | | Define config USB_STORAGE through defconfig for all Xilinx ZynqMP boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | xilinx: Sync defconfigs with the latest Kconfig layoutMichal Simek2016-08-02-54/+41
| | | | | | | | | | | | | | | | | | | | | Update Microblaze, Zynq and ZynqMP defconfigs to reflect latest Kconfig changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Wire up PSCI resetMichal Simek2016-08-02-0/+5
| | | | | | | | | | | | | | | | | | Using PSCI to reset the system. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodesMichal Simek2016-08-01-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial driver is getting clk information via DT that's why also clk node needs to have this flag. Different behavior was introduced by: "dm: Use dm_scan_fdt_dev() directly where possible" (sha1: 911954859d6dece49c3e4835faea004cfe392506) where simple-bus driver starts to call dm_scan_fdt_dev() which has additional logic around pre_reloc_only parameter which exclude clk nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | MAINTAINERS, git-mailrc: Update the mmc maintainerJaehoon Chung2016-08-02-3/+3
| | | | | | | | | | | | | | Update the mmc maintainer from Pantelis to me. Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Drop references to MAKEALL in the documentationSimon Glass2016-07-31-37/+15
| | | | | | | | | | | | | | | | It is confusing to mention MAKEALL when it is not the normal way of building U-Boot anymore. Update the documentation to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Drop the MAKEALL toolSimon Glass2016-07-31-850/+0
| | | | | | | | | | | | | | | | Buildman has been around for 3 years now. It has had a lot of use and testing. Perhaps it is time to remove MAKEALL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | buildman: Add a quick-start noteSimon Glass2016-07-31-0/+14
| | | | | | | | | | | | | | | | For those who just want to build a board, it is useful to see a quick hint right at the start of the documentation. Add a few commands showing how to download toolchains and build a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* | buildman: Avoid overwriting existing toolchain entriesSimon Glass2016-07-31-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code for setting up the toolchain config always writes the new paths to an item called 'toolchain'. This means that it will overwrite any existing toolchain item with the same name. In practice, this means that: buildman --fetch-arch all will fetch all toolchains, but only the path of the final one will be added to the config. This normally works out OK, since most toolchains are the same version (e.g. gcc 4.9) and will be found on the same path. But it is not correct and toolchains for archs which don't use the same version will not function as expected. Adjust the code to use a complete glob of the toolchain path. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | buildman: Drop the toolchain error when downloading toolchainsSimon Glass2016-07-31-7/+10
| | | | | | | | | | | | | | | | | | | | | | It doesn't make sense to complain about missing toolchains when the --fetch-arch option is being used. The user is presumably aware that there is a toolchain problem and is actively correcting it by running with this option. Refactor the code to avoid printing this confusing message. Signed-off-by: Simon Glass <sjg@chromium.org>
* | buildman: Fix a typo in TestSettingsHasPath()Simon Glass2016-07-31-1/+1
| | | | | | | | | | | | | | The function comment should say 'buildman'. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | buildman: Improve the toolchain progress/error outputSimon Glass2016-07-31-12/+21
| | | | | | | | | | | | | | | | | | | | Use colour to make it easier to see what is going on. Also print a message before downloading a new toolchain. Mention --fetch-arch in the message that is shown when there are no available toolchains, since this is the quickest way to resolve the problem. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | buildman: Allow the toolchain error to be suppressedSimon Glass2016-07-31-6/+14
| | | | | | | | | | | | | | | | | | When there are no toolchains a warning is printed. But in some cases this is confusing, such as when the user is fetching new toolchains. Adjust the function to supress the warning in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
* | buildman: Fix the 'help' test to use the correct pathSimon Glass2016-07-31-1/+1
| | | | | | | | | | | | | | When buildman is run via a symlink, this test fails. Fix it to work the same way as buildman itself. Signed-off-by: Simon Glass <sjg@chromium.org>
* | buildman: Automatically create a config file if neededSimon Glass2016-07-31-0/+44
| | | | | | | | | | | | | | | | | | | | If there is no ~/.buildman file, buildman currently complains and exists. To make things a little more friendly, create an empty one automatically. This will not allow things to be built, but --fetch-arch can be used to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | buildman: Tidy up the README a littleSimon Glass2016-07-31-23/+30
| | | | | | | | | | | | | | Tidy up some problems found by a recent review. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | libfdt: Introduce new ARCH_FIXUP_FDT optionMichal Simek2016-07-31-5/+17
|/ | | | | | | | | | Add new Kconfig option to disable arch_fixup_fdt() calls for cases where U-Boot shouldn't update memory setup in DTB file. One example of usage of this option is to boot OS with different memory setup than U-Boot use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-07-31-49/+1415
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| * rockchip: add support for rk3288 PopMetal boardjk.kernel@gmail.com2016-07-31-1/+729
| | | | | | | | | | | | | | | | | | PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add basic support for fennec-rk3288 boardjk.kernel@gmail.com2016-07-31-3/+630
| | | | | | | | | | | | | | | | | | | | Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: move evb board to rockchip folderjk.kernel@gmail.com2016-07-31-6/+6
| | | | | | | | | | | | | | | | The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is the real vendor name. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDRjk.kernel@gmail.com2016-07-31-3/+1
| | | | | | | | | | | | | | | | CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for fastboot. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: remove the duplicated macro configjk.kernel@gmail.com2016-07-31-4/+0
| | | | | | | | | | | | | | | | CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in config_distro_defaults.h, and we don't need them in SPL stage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: disable fastboot in SPL stagejk.kernel@gmail.com2016-07-31-1/+1
| | | | | | | | | | | | | | Reduce compilation time for SPL. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Revert "rockchip: Move the MMC setup check earlier"jk.kernel@gmail.com2016-07-31-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to setup sdmmc gpio, otherwise we will hit an error below: =>mmc info blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 - -1 0 - found uclass_find_device_by_seq: 0 1 - -1 -1 - -1 0 - not found fdtdec_get_int_array: interrupts get_prop_check_min_len: interrupts Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 Sending CMD0 dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * cosmetic: rockchip: rk3288: pinctrl: fix config symbol namingjk.kernel@gmail.com2016-07-31-1/+1
| | | | | | | | | | | | | | | | Revise config to CONFIG_ROCKCHIP_RK3288_PINCTRL. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * rockchip: add a dummy byte for the sdram-channel propertyjk.kernel@gmail.com2016-07-31-1/+2
| | | | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * rockchip: rk3288: Fix pinctrl for GPIO bank 0John Keeping2016-07-31-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit v1.1 at 2024-11-06 03:59:37 +0000