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* mx6sabresd: Access SRC_SBMR1 register via structureFabio Estevam2014-11-20-3/+2
| | | | | | | In U-boot it is preferred to access the register via structure pointer, so convert it such style. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* tqma6: use imx_ddr_sizeMarkus Niebel2014-11-20-1/+1
| | | | Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
* tqma6: add warning on failed setup_i2cMarkus Niebel2014-11-20-4/+16
| | | | | | | setup_i2c has a return value. Use it to give feedback on error. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
* tqma6: add missing includeMarkus Niebel2014-11-20-0/+1
| | | | | | Add include needed to have prototype for board_spi_cs_gpio Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
* tqma6: (cosmetic) remove CONFIG_FLASH_SECTOR_SIZEMarkus Niebel2014-11-20-14/+14
| | | | | | | | This is nowhere documented and only used by two other boards. Replace it with TQMA6_SPI_FLASH_SECTOR_SIZE. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
* mx6sabresd: Add mx6sabresd_spl_defconfig to MAINTAINERS entryFabio Estevam2014-11-20-0/+1
| | | | | | | Let's add mx6sabresd_spl_defconfig entry into MAINTAINERS, so that we avoid getting a warning that the mx6sabresd_spl is not maintained. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sxsabresd: Simplify the return value of setup_fec()Fabio Estevam2014-11-20-6/+1
| | | | | | | We can simply the return the value from enable_fec_anatop_clock() to make the code smaller and simpler. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6slevk: Simplify the return value of setup_fec()Fabio Estevam2014-11-20-6/+1
| | | | | | | We can simply the return the value from enable_fec_anatop_clock() to make the code smaller and simpler. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sabresd: State that only mx6q is supported in SPLFabio Estevam2014-11-20-4/+2
| | | | | | Make clear that current SPL code only supports the mx6q variant. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx53loco: Fix error handling in board_mmc_init()Fabio Estevam2014-11-20-4/+6
| | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* wandboard: Fix error handling in board_mmc_init()Fabio Estevam2014-11-20-4/+6
| | | | | | | | When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* tools/msximage.c: fix warning about nptr possibly uninitializedAlbert ARIBAUD2014-11-20-1/+1
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* mx6qsabreauto: Add parallel NOR flash supportFabio Estevam2014-11-20-1/+89
| | | | | | | | | | | | | | | | | | | | | mx6sabreauto boards come with 32 MiB of parallel NOR flash. Add support for it: U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB Flash: 32 MiB NAND: 0 MiB Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is not used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: add weim registersFabio Estevam2014-11-20-0/+37
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: consolidate set_chipselect_size functionFabio Estevam2014-11-20-41/+39
| | | | | | | | | | Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Use a common SPL configuration fileFabio Estevam2014-11-20-40/+4
| | | | | | | | | Many boards use a minimal .cfg file in the SPL case. Introduce spl_sd.cfg so that we can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* novena: Move the DCD settings to spl codeFabio Estevam2014-11-20-31/+28
| | | | | | | | | | | | mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de>
* gw_ventana: Move the DCD settings to spl codeFabio Estevam2014-11-20-48/+28
| | | | | | | | | | | mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sabresd: Move the DCD settings to spl codeFabio Estevam2014-11-20-38/+27
| | | | | | | | | | | mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: fix exception vectors relocation in imx27Albert ARIBAUD2014-11-20-28/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ff46cc4 fixed exception vectors setting in the general ARM case, by either copying the exception and indirect vector tables to normal (0x00000000) or high (0xFFFF0000) vectors address, or setting VBAR to U-Boot's base if applicable. i.MX27 SoC is ARM926E-JS, thus has only normal and high options, but does not provide RAM at 0xFFFF0000 and has only ROM at 0x00000000; it is therefore not possible to move or change its exception vectors. Besides, i.MX27 ROM code does provide an indirect vectors table but at a non-standard address and with the reset and reserved vectors missing. Turn the current vector relocation code into a weak routine called after relocate_code from crt0, and add strong version for i.MX27. Series-Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Tested-by: Philippe Reynes <tremyfr@gmail.com> Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
* cosmetic: arm: fix whitespace in arch/arm/lib/relocate.SAlbert ARIBAUD2014-11-20-4/+4
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* imx: mx6slevk: Change default mmcdev to USDHC2 deviceYe.Li2014-11-20-1/+1
| | | | | | | Since USDHC1 and USDHC3 added, the dev index for USDHC2 changed to 1. So modify the default mmcdev in environment variables to dev 1. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx:mx6sxsabresd fix pfuz probe failedPeng Fan2014-11-20-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The PFUZ probe failed with the following msg: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=0 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=1 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=2 i2c_init_transfer: give up i2c_regs=021a0000 Can't find PMIC:PFUZE100 " board_early_init_f is too early to call i2c related setting, because init_func_i2c is called after board_early_init_f being invoked. Thus move setup_i2c into board_init. Also PFUZ is connected to I2C bus 0, so change "1" -> "0". Using this patch PFUZ can be correctly probed: "PMIC: PFUZE100 ID=0x11" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* ARM: mxs: tools: Add support for boot progress display flagAlexey Ignatov2014-11-20-12/+27
| | | | | | | | mkimage -T mxs now support new flag in config file: DISPLAYPROGRESS - makes boot process print HTLLC characters for each BootROM instruction. Signed-off-by: Alexey Ignatov <lexszero@gmail.com>
* ARM: atmel: add sama5d4 xplained ultra board supportBo Shen2014-11-17-0/+583
| | | | | | | | | | | The code for this board supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display (optional, disabled by default) - Support ethernet - Support USB mass storage Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: add sama5d4ek board supportBo Shen2014-11-17-9/+868
| | | | | | | | | | | The code for this board supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display - Support ethernet - Support USB mass storage Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* net: macb: enable GMAC IP without GE feature supportBo Shen2014-11-17-1/+7
| | | | | | | | | | The User Register in GMAC IP is used to select interface type. When with GE feature, it is used to select interface between RGMII and GMII. If without GE feature, it is used to select interface between MII and RMII. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel_nand: runtime to build gf table for pmeccJosh Wu2014-11-17-1/+78
| | | | | | | | | | | | | | | As in SAMA5D4 SoC, the gf table in ROM code can not be seen. So, when we try to use PMECC, we need to build it when do initialization. Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it is defined we will build gf table runtime. The PMECC use the BCH algorithm, so based on the build_gf_tables() function in lib/bch.c, we can build the Galois Field lookup table. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, spl, at91: add spl support for the corvus boardHeiko Schocher2014-11-17-18/+151
| | | | | | | | | | | | | | replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91, spl: add spl support for the taurus boardHeiko Schocher2014-11-17-13/+127
| | | | | | | | | | | | | | replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, spl, at91: add at91sam9260 and at91sam9g45 spl supportHeiko Schocher2014-11-17-97/+430
| | | | | | | | | | | add support for using spl code on at91sam9260 and at91sam9g45 based boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [adopt Bo's change in spl.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, mtd, nand, atmel_nand: invert device ready pin logicHeiko Schocher2014-11-17-3/+3
| | | | | | | | | | | device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, nand, atmel_nand: add erase one block functionHeiko Schocher2014-11-17-0/+34
| | | | | | | | | | | erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel_nand: add missing includeHeiko Schocher2014-11-17-0/+1
| | | | | | | | | | | using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, nand: add option to boot raw u-boot.bin image onlyHeiko Schocher2014-11-17-5/+28
| | | | | | | | | | | enable to boot only a raw u-boot.bin image from nand with the CONFIG_SPL_NAND_RAW_ONLY define. This option saves space on boards where spl space is low. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE defineHeiko Schocher2014-11-17-0/+1
| | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45Heiko Schocher2014-11-17-2/+15
| | | | | | | | | | | | - compile mpddrc ram init code also for AT91SAM9M10G45 based boards. - in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED in the cr configuration Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91, mpddrc: fix typo in ddr2_init()Heiko Schocher2014-11-17-1/+1
| | | | | | | | | | | use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: add spi dataflash support for the taurus boardHeiko Schocher2014-11-17-0/+28
| | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common headerHeiko Schocher2014-11-17-13/+4
| | | | | | | | | | | | move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value). Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: generate boot.bin file for all atmel SoCHeiko Schocher2014-11-17-3/+5
| | | | | | | | | | generate the boot.bin file for all atmel SoC (arm920, arm926, armv7) Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: spl: make css field configurableBo Shen2014-11-17-2/+4
| | | | | | | | | The clock source for master clock can be slow clock, main clock, plla clock or upll clock. So, make the clock source selection field in mckr can be configured. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: spl: make initialization more stableBo Shen2014-11-17-0/+4
| | | | | | | | We need to make sure the main clock ready field in MCFR is set after switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: at91 series: convert to generic boardBo Shen2014-11-17-0/+6
| | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* net: macb: write mac address when initializationBo Shen2014-11-17-0/+9
| | | | | | | | | | | | | | | | | When boot up without mac address setting, it will give the warning message like: "Warning: failed to set MAC address", however when execute network related command, it still execute them without any warning information. With this patch, it will exit directly with following information: "gmac0: mac address is not valid" It also solve the problem after bootup then set mac address and the mac address won't set to net device issue. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2014-11-17-107/+93
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| * sh: Move SH_32BIT to KconfigNobuhiro Iwamatsu2014-11-17-4/+13
| | | | | | | | | | | | | | This moves SH_32BIT to Kconfig, and removes SH_32BIT from config files. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: define CONFIG_CPU_SH4A for some boardsMasahiro Yamada2014-11-13-7/+7
| | | | | | | | | | | | | | | | Precisely, these boards are SH4A rather than SH4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: consolidate CONFIG_SYS_CPU definesMasahiro Yamada2014-11-13-66/+8
| | | | | | | | | | | | | | | | | | | | Now each board selects one of CONFIG_CPU_SH2, CONFIG_CPU_SH3, CONFIG_CPU_SH4, so let's move CONFIG_SYS_CPU definition to arch/sh/Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: move CONFIG_{SH2, SH2A, SH3, SH4} to KconfigMasahiro Yamada2014-11-13-18/+53
| | | | | | | | | | | | | | | | | | | | | | This commit moves CONFIG_SH2, CONFIG_SH2A, CONFIG_SH3, CONFIG_SH4 to Kconfig renaming into CONFIG_CPU_SH2, CONFIG_CPU_SH2A, CONFIG_CPU_SH3, CONFIG_CPU_SH4, respectively because arch/sh/Kconfig of Linux uses CONFIG_CPU_SH* convention. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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