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* | powerpc: ppc4xx: remove zeus supportMasahiro Yamada2015-09-02-968/+1
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove sbc405 supportMasahiro Yamada2015-09-02-1148/+1
| | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | powerpc: ppc4xx: remove pcs440ep supportMasahiro Yamada2015-09-02-1930/+1
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove p3p440 supportMasahiro Yamada2015-09-02-592/+1
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove lwmon5 supportMasahiro Yamada2015-09-02-2128/+2
| | | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Remove CONFIG_LWMON5 references. (Also, remove undefined CONFIG_WD_MAX_RATE while I am here.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove csb272, csb472 supportMasahiro Yamada2015-09-02-1324/+1
| | | | | | | | | | | | | | | | These have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tolunay Orkun <torkun@nextio.com>
* | powerpc: ppc4xx: remove alpr supportMasahiro Yamada2015-09-02-1037/+2
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | ea20: Convert to generic boardStefano Babic2015-09-02-0/+2
| | | | | | | | | | | | | | Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | serial: drop redundant depends onMasahiro Yamada2015-09-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | SANDBOX_SERIAL depends on SANDBOX, and SANDBOX selects DM. So, "SANDBOX_SERIAL depends on DM" is redundant. Likewise, UNIPHIER_SERIAL depends on ARCH_UNIPHIER, and ARCH_UNIPHIER selects DM_SERIAL. So, "UNIPHIER_SERIAL depends on DM_SERIAL" is redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-09-02-53/+193
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| * | powerpc/t1023rdb: change default core frequency to 1200MHzShengzhou Liu2015-09-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Per new requirement, change default core frequency from previous 1400MHz to 1200MHz to save power. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: convert selected boards to generic board structureYork Sun2015-09-01-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Convert MPC8540ADS, MPC8541CDS, MPC8544CDS, MPC8548CDS, MPC8555CDS, MPC8560ADS, MPC8568MDS, MPC8569MDS, MPC8610HPCD to use generic board structure. Signed-off-by: York Sun <yorksun@freescale.com>
| * | net/fman: Support both new and legacy FMan CompatiblesIgal Liberman2015-09-01-35/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Igal Liberman <igal.liberman@freescale.com> Tested-by: Xing Lei <xing.lei@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ramYork Sun2015-09-01-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write through cache on E6500. L2 cache is enabled to to hold the data. This patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
| * | powerpc: configs: Fix init_ram physical address for several boardsYork Sun2015-09-01-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | For e6500 and e5500 SoCs, it was intended to put init_ram address in ccsr reserved space. It is no longer true since SerDes module took the space. Move it to another reserved space at CCSR + 0x03c000. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/defconfig: Rename defconfig file for T1040QDS/T1024QDS DDR4 targetsYork Sun2015-09-01-3/+3
| | | | | | | | | | | | | | | | | | | | | Previously the DDR4 targets were named with _D4. Rename them with _DDR4 for easy identification. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1024qds: Add missing T1024QDS_DDR4_defconfigYork Sun2015-09-01-0/+5
| |/ | | | | | | | | | | | | T1024QDS with DDR4 has been supported. Add the missing defconfig. Signed-off-by: York Sun <yorksun@freescale.com> CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-02-605/+4146
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| * | imx: vf610 add get_cpu_revPeng Fan2015-09-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we need to support runtime check for different drivers, we need to add get_cpu_rev for vf610, otherwise there will be build errors. This patch introduces a dummy CPU id which is not read from chip silicon. Later when we can get the real id from chip, can fix the value of MXC_CPU_VF610 then. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Suggested-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxc: ocotp fix hole in shadow registersPeng Fan2015-09-02-6/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: mx6: cm-fx6: switch to usb kbd polling via int queueNikita Kiryanov2015-09-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE works better than CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP (keyboards that previously didn't work such as Microsoft Comfort Curve 1000 now do work, and it's also faster). Switch to CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | arm: mx6: cm-fx6: print PCB revisionNikita Kiryanov2015-09-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Print board revision for cm-fx6. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | arm: mx6: cm-fx6: force host mode on usb controllerNikita Kiryanov2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some CM-FX6 modules U-Boot attempts to configure the usb0 controller in device mode, which renders it unavailable: USB0: Port not available. and also causes usb stop to report an error EHCI failed to shut down host controller. This happens mostly on MX6 Dual based modules, and is caused by the USBPHY_CTRL register reporting USBPHY_CTRL_OTG_ID to be 1, even when it is pulled down. Since we do not support device mode in cm-fx6 u-boot, force all controllers to be configured as hosts. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | arm, imx6: add aristainetos 2b board versionHeiko Schocher2015-09-02-14/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is a 2b board version of the aristainetos2 board. Differences to the v2: - spi cs for the nor flash and display controller changed - some pinmux changes - LED gpio settings changed Signed-off-by: Heiko Schocher <hs@denx.de>
| * | video, lg4573: make spi bus and cs configurableHeiko Schocher2015-09-02-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | make the spi bus and the spi chipselect configurable for the lg4573 driver. Use it on the aristainetos boards. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | imx: mx6ul_14x14_evk discard MX6UL from CONFIG_SYS_EXTRA_OPTIONSPeng Fan2015-09-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Discard MX6UL from CONFIG_SYS_EXTRA_OPTIONS, since we default select MX6UL for mx6ul_14x14_evk board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: mx6ul_14x14_evk select MX6ULPeng Fan2015-09-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to expose SoC choice to user, we already got the SoC according to the build target. So default "select MX6UL" for MX6UL_14x14_EVK target. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: Add SYS_L2CACHE_OFF Kconfig entryPeng Fan2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6UL, SYS_L2CACHE_OFF is selected, but there is no Kconfig entry for SYS_L2CACHE_OFF. Then "select SYS_L2CACHE_OFF" does not effect for i.MX6UL, which is not expected. Since SYS_L2CACHE_OFF is mainly used by ARM architecture, add it to arch/arm/Kconfig. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6slevk: add SPL supportPeng Fan2015-09-02-1/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPL boot support for mx6slevk board. 1. Introduce a configuration file mx6slevk_spl_defconfig. 2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE. 3. Include imx6_spl.h and related SPL macro in mx6slevk.h. 4. select SUPPORT_SPL for TARGET_MX6SLEVK. 5. Add SPL board code to do related initialization. Boot Log: U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000) CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 50C Reset cause: POR Board: MX6SLEVK I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: mx6: ddr: add LPDDR2 supportPeng Fan2015-09-02-4/+311
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add LPDDR2 support: 1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2. 2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to mx6_ddr3_cfg, but still keep it a single one for easy to choose parameters for LPDDR2. 3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC. 4. Update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | imx: mx6: ddr init MMDC according to ddr_typePeng Fan2015-09-02-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper. The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg when ddr_type is for DDR3. Later we can use ddr_type to initialize MMDC for LPDDR2. Initialize ddr_type for different boards which enable SPL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfoPeng Fan2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ddr_type entry for mx6_ddr_sysinfo. It will be used for differenrate DDR3 and LPDDR2. Introduce an enum type for ddr_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | imx: mx6: ddr add mpzqlp2ctl entryPeng Fan2015-09-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add mpzqlp2ctl entry for mx6_mmdc_calibration. MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | imx: mx6: ddr add dram io configuration and header file for i.MX6SLPeng Fan2015-09-02-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs. Add a new function mx6sl_dram_iocfg to configure dram io. Add header file to define macros for register address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: ddr correct tRFC and tXSPeng Fan2015-09-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To Chip density 4Gb, tRFC should be 300ns, see "Table 61 — Refresh parameters by device density" of JESD79-3E. tXS(min) is max(5nCK, tRFC(min) + 10ns). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: ddr no support MMDC1 for i.MX6SLPeng Fan2015-09-02-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: ddr add more register entry for mmdc_p_regsPeng Fan2015-09-02-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add more register entry for MMDC structure. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | tbs2910: remove SYS_SOC from board specific KconfigSoeren Moch2015-09-02-3/+0
| | | | | | | | | | | | | | | | | | | | | SYS_SOC is already defined in arch/arm/cpu/armv7/mx6/Kconfig, no need to define it again Signed-off-by: Soeren Moch <smoch@web.de>
| * | tbs2910: remove deprecated CONFIG_SYS_EXTRA_OPTIONSSoeren Moch2015-09-02-1/+6
| | | | | | | | | | | | | | | | | | move options from CONFIG_SYS_EXTRA_OPTIONS to board specific Kconfig Signed-off-by: Soeren Moch <smoch@web.de>
| * | tbs2910: use full name in Kconfig board selectionSoeren Moch2015-09-02-1/+1
| | | | | | | | | | | | Signed-off-by: Soeren Moch <smoch@web.de>
| * | imx: fec: add MAC reading from eFuses to READMEOlaf Mandel2015-09-02-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the documentation of the fec_mxc configuration by describing its ability to read the ethaddr MAC address from the SoC eFuses. Also add an example how to program the fuses for an imx5 to clarify the byte order. Cc: Stefano Babic <sbabic at denx.de> Cc: Marek Vasut <marex at denx.de> Signed-off-by: Olaf Mandel <o.mandel at menlosystems.com>
| * | arm, imx6: aristainetos board updatesHeiko Schocher2015-09-02-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some small updates for the aristainetos boards: - fix display timings for the aristainetos board - fix pinmux for the aristainetos board - fix pinmux for the aristainetos2 board - fix default environment Signed-off-by: Heiko Schocher <hs@denx.de>
| * | imx: mx6sxsabresd: enable CONFIG_SPL_FAT_SUPPORTPeng Fan2015-09-02-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable CONFIG_SPL_FAT_SUPPORT to load u-boot.img from FAT partition. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ul_14x14_evk add ENET supportPeng Fan2015-09-02-1/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add enet support for mx6ul_14x14_evk board: 1. add pinmux settings 2. implement board_eth_init 3. implement board_phy_config Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: ocotp: mxc add i.MX7D supportAdrian Alonso2015-09-02-1/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Ocotp of i.MX7D has different operation rule. This patch is to add support for i.MX7D ocotp. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-02-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: iomux-v3: add imx7d support for iomuxcAdrian Alonso2015-09-02-0/+1377
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add imx7d support for iomux controller * imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr (0x302C0000) each conroller provides control and mux mode pad registers but shares iomuxc input select register with iomuxc-lpsr IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings for iomuxc-lpsr pads. * Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * | power: pmic: add pfuze3000 supportAdrian Alonso2015-09-02-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | * Add pmic pfuze3000 support, implement power_pfuze3000_init to be used in power_init_board callback function. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | net: fec: do not access reserved register for i.MX6ULPeng Fan2015-09-02-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: clock support enet2 anatop clock supportPeng Fan2015-09-02-12/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-07 13:37:32 +0000