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| * zynqmp: sdhci: Remove the quirk SDHCI_QUIRK_NO_CDSiva Durga Prasad Paladugu2015-04-29-1/+1
| | | | | | | | | | | | | | | | Remove the quirk SDHCI_QUIRK_NO_CD as it is not required. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add support for R5 sw loadingMichal Simek2015-04-29-3/+285
| | | | | | | | | | | | | | Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * zynqmp: caches: Enable dcache for zynqmpSiva Durga Prasad Paladugu2015-04-29-1/+165
| | | | | | | | | | | | | | | | Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: slcr: Disable all level shiftersSiva Durga Prasad Paladugu2015-04-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | Disable all level shifters before enabling the PS-to-PL level shifters as it would be good to disable all level shifters before enabling the PS-to-PL in order to ensure that it is in proper state Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: drop legacy ps7_init.c/h supportMasahiro Yamada2015-04-29-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We are about to change the location for ps7_init files, breaking the current work-flows. It is good time to drop the legacy ps7_init.c/h support. Going forward, please use ps7_init_gpl.c/h all the time. If you are still using old Xilinx tools that are only able to generate ps7_init.c/h, rename them into ps7_init_gpl.c/h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Add Zynq PicoZed board supportNathan Rossi2015-04-29-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PicoZed is a System-on-Module board which is marketed as part of the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000 processor. This patch adds support that covers all the variants of the PicoZed including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This patch set however only covers support for the System-on-Module and does not cover any extra components that are available on carrier boards (except those that are fanned out of the module itself). More information on this board, its variants and available carrier boards is available at: http://zedboard.org/product/picozed Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * serial: zynq: Add support for slow emulation platformMichal Simek2015-04-29-1/+7
| | | | | | | | | | | | | | | | On slow platforms not all baudrate setting is valid. Check it directly in the driver and setup maximum possible frequency. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Enable GPIO driver and GPIO commandsMichal Simek2015-04-29-0/+3
| | | | | | | | | | | | Enable GPIO driver and GPIO commands. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * gpio: add Xilinx Zynq PS GPIO driverAndrea Scian2015-04-29-0/+287
| | | | | | | | | | | | | | | | | | Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian <andrea.scian@dave.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-04-29-1/+1
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| * | microblaze: Fix EMAC Lite initializationNathan Rossi2015-04-29-1/+1
| |/ | | | | | | | | | | | | | | | | | | It is possible for CONFIG_XILINX_EMACLITE to be defined without XILINX_EMACLITE_BASEADDR being defined as the EMAC Lite driver support OF init. Check that the driver is enabled and the base address is available before initializing with a static base address. Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-socfpgaTom Rini2015-04-28-51/+197
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| * | socfpga: implement arria V socdk SPI flash config in dtsPavel Machek2015-04-27-0/+24
| | | | | | | | | | | | | | | | | | | | | Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek <pavel@denx.de>
| * | socfpga: implement socdk SPI flash config in dtsPavel Machek2015-04-24-0/+24
| | | | | | | | | | | | | | | | | | | | | SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: spl: Add stub sdram.hMarek Vasut2015-04-21-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still need to be able to compile the codebase. Introduce stub functions which temporarily supplement the missing SDRAM setup functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * | spi: Add Cadence QSPI controller Kconfig entryMarek Vasut2015-04-21-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * | spi: Add Designware SPI controller Kconfig entryMarek Vasut2015-04-21-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DWC SPI controller Kconfig entry. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * | arm: socfpga: spl: update peripheral pll for dev kitDinh Nguyen2015-04-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | "commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration" mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct value should be 79. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: add board_init_f to SPLDinh Nguyen2015-04-21-0/+29
| | | | | | | | | | | | | | | | | | | | | Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: spl: Add s_init stubDinh Nguyen2015-04-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a stub s_init function in the board file. The reason why the stub function is needed is that most of the work is now being done in board_init_f(), there is no need for the SPL to do anything s_init(). However, since lowlevel_init() is still branching to s_init(), we need stub function for now, until lowlevel_init() morphs into s_init(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: fix uart0 pin mux configurationDinh Nguyen2015-04-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK. This fixes it up so UART0 is working again. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: Add SDRAM checkDinh Nguyen2015-04-21-0/+6
| | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl mallocDinh Nguyen2015-04-21-1/+1
| | | | | | | | | | | | | | | | | | | | | We need to adjust the SYS_INIT_RAM_SIZE to have room for the SPL_MALLOC_SIZE. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.hDinh Nguyen2015-04-21-0/+5
| | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: Use common lowlevel_initDinh Nguyen2015-04-21-47/+1
| | | | | | | | | | | | | | | | | | | | | For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the SoCFPGA lowlevel_init.S file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: printout sdram sizeDinh Nguyen2015-04-21-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: spl: add sdram init and calibrationDinh Nguyen2015-04-21-0/+13
| | | | | | | | | | | | | | | | | | Add a call to checkboard along with sdram intilialization and calibration. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: allow bootrom to enable IOs after warm resetDinh Nguyen2015-04-21-0/+13
| | | | | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: spl: Add call to timer_initDinh Nguyen2015-04-21-0/+2
| | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: enable sdram, timer and uartDinh Nguyen2015-04-21-0/+4
| | | | | | | | | | | | | | | | | | | | | Add the calls in the spl_board_init to enable SDRAM, timer, and UART. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: add functions to bring sdram, timer, and uart out of resetDinh Nguyen2015-04-21-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | These functions will be needed for use by the SPL for enabling the console and sdram initialization. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KBDinh Nguyen2015-04-21-0/+1
| | | | | | | | | | | | | | | | | | The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-dmTom Rini2015-04-28-4/+8
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| * | | dm: core: Correct bug introduced in uclass_first/next_device()Simon Glass2015-04-28-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions now rely on uclass_find_first/next_device() and assume that they will either return failure (-ve error code) or a device. In fact, coming to the end of a list is not considered failure and they return 0 in that case. The logic to deal with this was replaced in commit acb9ca2a with just using uclass_get_device_tail(). Add back the missing logic. This bug was caught by unit tests but since they were broken for other reasons at the time, this was not noticed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | serial: ns16550: Remove hard-coded baud_divisor settingAxel Lin2015-04-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: drop device removal error path correctlyMasahiro Yamada2015-04-28-3/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | Trivial bug fix for commit 5a87c4174d18 (dm: core: Drop device removal error path when not supported). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-28-213/+1480
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| * | mx6cuboxi: Load the correct 'fdtfile' variableFabio Estevam2015-04-27-3/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hardcoding the 'fdtfile' variable, let's detect the SoC and board variant on the fly and change the dtb name. Based on the scheme done on am335x board. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-By: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mx6cuboxi: Use more standard namings for fdt variablesFabio Estevam2015-04-27-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | README file suggests to use 'fdtfile' for the dtb file name and 'fdt_addr_r' for the dtb address in RAM, so do as suggested. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mx6cuboxi: Differentiate Cubox-i and HummingboardFabio Estevam2015-04-27-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce is_hummingboard() function that reads GPIOs that can distinguish between Cubox-i and Hummingboard. Print the board name accordingly. Based on a patch from Rabeeh Khoury. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mx6cuboxi: Introduce multi-SoC supportFabio Estevam2015-04-27-9/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite, mx6dual and mx6quad. Add support for the different SoC/memory sizes combinations. DDR initialization values were extracted from Solid-run internal U-boot. Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mx6cuboxi: Prepare for multi SoC supportFabio Estevam2015-04-27-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite, mx6dual and mx6quad. Use IOMUX_PADS() macro in order to prepare for the multi-SoC support. Also pass 'MX6QDL' in the defconfig to indicate it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mx6cuboxi: Fix the defconfig nameFabio Estevam2015-04-27-1/+1
| | | | | | | | | | | | | | | | | | | | | The correct name of the defconfig file is 'mx6cuboxi_defconfig'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mx6sabresd: Remove uneeded ifdefFabio Estevam2015-04-22-4/+0
| | | | | | | | | | | | | | | | | | RTT_NOM_120OHM is not defined, so remove its ifdef. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6sabresd: Fix SPL memory descriptionFabio Estevam2015-04-22-4/+5
| | | | | | | | | | | | | | | | | | | | | mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus and 2GiB, so fix the width and density fields accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | nitrogen6x: allow gzipped bitmap displayEric Nelson2015-04-22-0/+3
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | iMX: Fix compilation error when enabling SECURE_BOOTgaurav rana2015-04-22-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the compilation of file fsl_validate.c in MACRO CONFIG_CMD_ESBC_VALIDATE. This file should be compiled only when the above MACRO is defined This caused a break in compilation of iMX platforms when compiling for SECURE_BOOT Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
| * | arm: mx6: tqma6: Extract baseboard configs into separate config fileStefan Roese2015-04-22-41/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extracts all baseboard specific defines into a separate config file. This makes it easier to add other baseboards that use the TQMa6 SoM. This patch will be used by the upcoming WRU-IV board support which also uses the TQMa6 SoM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de> Acked-By: Markus Niebel <Markus.Niebel@tq-group.com>
| * | power: pfuze100: fix LDO_EN bit valueTim Harvey2015-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The LDO_EN is bit 4, not value 4. This is only used on the Ventana boards so we will change it in the header as the other values there are in terms of values and not bit numbers. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: ventana: Update missing memory/calib handlingPushpal Sidhu2015-04-22-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit combines catching missing memory and calibration data into one if() block. It further prints pertinent information in determining why the failure occurred. Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
generated by cgit v1.1 at 2024-10-16 15:26:36 +0000