summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
...
| * mips: Drop JZ4740 remnantsMarek Vasut2016-05-26-1158/+0
| | | | | | | | | | | | | | | | Remove the remnants of JZ4740 support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * mips: Allow overriding start.S in SPLMarek Vasut2016-05-26-0/+6
| | | | | | | | | | | | | | | | | | | | Certain chips, like the JZ47xx, have extreme size constraints on the SPL size and require custom start.S . Allow overriding the start.S the same way ARM MXS does it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Move CONFIG_SYS_TEXT_BASE to KconfigPaul Burton2016-05-26-24/+29
| | | | | | | | | | | | | | | | | | Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board Kconfig files matching what was present in their config headers. This will make it cleaner to conditionalise the value for Malta based on 32 vs 64 bit builds. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: Use device model & tree for UARTPaul Burton2016-05-26-6/+41
| | | | | | | | | | | | | | | | | | | | | | Make use of device model & device tree to probe the UART driver. This is the initial step in bringing Malta up to date with driver model, and allows for cleaner handling of the different I/O addresses for different system controllers by specifying the ISA bus address instead of a translated memory address. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * malta: Tidy up UART address selectionPaul Burton2016-05-26-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | The address of the UART differs based upon the system controller because it's actually within the I/O port region, which is in a different location for each system controller. Rather than handling this as 2 UARTs with the correct one selected at runtime, use I/O port accessors for the UART such that access to it gets translated into the I/O port region automatically. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * dm: ns16550: Don't map_physmem for I/O portsPaul Burton2016-05-26-2/+8
| | | | | | | | | | | | | | | | | | | | | | If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * fdt: Document the rest of struct of_busPaul Burton2016-05-25-0/+19
| | | | | | | | | | | | | | | | Provide some documentation for the fields of struct of_bus, for consistency with that provided for the new match field. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fdt: Support for ISA bussesPaul Burton2016-05-25-3/+121
| | | | | | | | | | | | | | | | | | | | Support ISA busses in much the same way as Linux does. This allows for ISA bus addresses to be translated, and only if CONFIG_OF_ISA_BUS is selected in order to avoid including the code in builds which won't need it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm64: fix arm64 Linux boot image header field sizesAndre Przywara2016-05-25-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The arm64 Linux boot protocol [1] describes the fields in the Image header as being 64-bit little endian values. So fix the endianess conversion to use 64-bit sized operations, for both image_size and text_offset. Also we use a local variable for the image_size to avoid both writing to the header and also accessing it after we actually unmapped it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.txt
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-05-25-1225/+740
|\ \
| * | sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulatorsStefan Mavrodiev2016-05-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sets LDO3 and LDO4 regulators at 2.8V. In the current config these are off. This causes kernel to hang during axp209 initialization. Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Enable a bunch of commands by default on sunxiHans de Goede2016-05-25-943/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently a set of CONFIG_CMD_FOO defines was moved from being defined in config_distro_defaults to Kconfig, and added to all sunxi defconfigs to compensate. Instead of explictly selecting these in all sunxi defconfigs, simply always select these for sunxi boards. This makes the defconfigs simpler and ensures a consistent set of available commands across all sunxi boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | arm64: Pine64: update FDT filesAndre Przywara2016-05-25-199/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The originally committed .dts files for the Pine64 were from an early proof-of-concept version and should have never been committed upstream. Replace them with much more mature versions, which also use a different naming scheme. Please note that at this point there is at least one binding which has not been agreed upon, so this is subject to change. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | arm64: sunxi: adjust default load addressesAndre Przywara2016-05-25-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As arm64 has slightly different expectations about load addresses, lets use a different set of default addresses for things like the kernel. As arm64 kernels don't come with a decompressor right now, reserve some more space for really big uncompressed kernels. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | Revert "sunxi: Reserve ATF memory space on A64"Andre Przywara2016-05-25-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Trusted Firmware (ATF) code now lives in SRAM on the Pine64/A64, so we can claim the whole of DRAM for OS use. This reverts commit 3ffe39ed2b66af71c7271d0cef2a248b5bf7dfdb. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Properly announce BOOT_DEVICE_BOARD as "FEL"Bernhard Nortmann2016-05-25-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This addresses a cosmetic issue when booting a sunxi device over USB (FEL mode), where the SPL currently would just print "Trying to boot from ". The patch fixes that to properly read "Trying to boot from FEL". Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Increase SPL header size to 64 bytes to avoid code corruptionSiarhei Siamashka2016-05-25-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: power: add AXP809 supportChen-Yu Tsai2016-05-25-34/+367
| | | | | | | | | | | | | | | | | | | | | | | | The A80 uses the AXP809 as its primary PMIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Implement poweroff support for axp818 pmicChen-Yu Tsai2016-05-25-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Adds poweroff support for axp818 pmic. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Enable AXP818 SW for Sinovoip BPI M3Chen-Yu Tsai2016-05-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SW output of the PMIC supplies the ethernet PHY with power. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: power: axp818: Add support for switch SWChen-Yu Tsai2016-05-25-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | The AXP818 has a switchable output, SW. This is commonly used for controlling power to the LCD backlight. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | power: axp818: Fix typo for fldo2 Kconfig descriptionChen-Yu Tsai2016-05-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Description said eldo2 instead of fldo2, a copy-paste error. Fixes: 38491d9c6515 ("power: axp818: Add support for FLDOs") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | power: axp221: Remove switch case to simplify axp_set_eldoChen-Yu Tsai2016-05-25-20/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ELDO enable bits and registers are contiguous for axp221. Instead of a switch case testing against the index, just use the index to shift the bit or register offset. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Disable VIDEO for SoCs without display supportChen-Yu Tsai2016-05-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The newer chips use a newer display pipeline, which is not supported. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCsChen-Yu Tsai2016-05-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | A83T, H3, and A64 have a dedicated pin for card detect on the PF pingroup. This is used in all designs. Set it as the default. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Sort SoC variants by family (sunXi) first, chip name secondChen-Yu Tsai2016-05-25-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | In most other places, we sort SoC descriptions by family (sunXi) first, then by the chip name (A20). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: make SoC variant choice mandatoryChen-Yu Tsai2016-05-25-1/+0
| |/ | | | | | | | | | | | | | | | | The user should always select an SoC variant to support. Not choosing one doesn't make sense for a bootloader. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-25-22/+426
|\ \
| * | ARM: uniphier: add EHCI nodes for PH1-LD11Masahiro Yamada2016-05-26-0/+48
| | | | | | | | | | | | | | | | | | Make the USB feature really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | clk: uniphier: add Media I/O clock driver support for PH1-LD11Masahiro Yamada2016-05-26-0/+4
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PH1-LD11 SoC supportMasahiro Yamada2016-05-26-4/+354
| | | | | | | | | | | | | | | | | | This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename UMC register macros of PH1-LD20Masahiro Yamada2016-05-26-4/+4
| | | | | | | | | | | | | | | | | | Correct some register names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename umc-ld20-regs.h to umc64-regs.hMasahiro Yamada2016-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This header will be shared between PH1-LD11 and PH1-LD20 (and hopefully new ARMv8 SoCs developed in the future), so umc64-regs.h would be a better fit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: clean up boot mode tablesMasahiro Yamada2016-05-26-13/+13
| | | | | | | | | | | | | | | | | | Tidy up alignment of open parentheses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: disable cache in SPL of PH1-LD20Masahiro Yamada2016-05-26-0/+2
| |/ | | | | | | | | | | | | | | The Boot ROM has enabled D-cache and MMU setting DDR memory area as Normal Memory in its page table. Disable D-cache and MMU before jumping to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-3/+39
|\ \ | |/ |/|
| * powerpc:t4240: MAC9 and MAC10 should not be identified as 1G interface in ↵Ying Zhang2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | some case When using rcw protocols to support 10G on MAC9 and MAC10, these MACs should not be identified as 1G interface, otherwise, one MAC will be listed as two Ethernet ports. For example, MAC9 will be listed as FM1@TGEC1 and FM1@DTSEC9. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDBYing Zhang2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5, FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6. Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cacheAneesh Bansal2016-05-24-0/+23
| | | | | | | | | | | | | | | | | | | | While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/t2080qds: Enable qixis commands to reboot from NAND and SDYork Sun2016-05-19-0/+4
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc/t208xrdb: Update MAINTAINERS fileYork Sun2016-05-19-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc/t208xqds: Update MAINTAINERS fileYork Sun2016-05-19-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc: Disable flush or invalidate dcache by range for some SoCsYork Sun2016-05-19-0/+4
| | | | | | | | | | | | | | | | | | | | | | Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-op for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues when the dcache is flushed. While the root cause is under investigation, disable these functions for affected SoCs so various drivers can work. Signed-off-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-218/+631
|\ \
| * | armv8: ls1043ardb: enable scsi command and pcie to sata converterPo Liu2016-05-18-0/+21
| | | | | | | | | | | | | | | | | | | | | Enable scsi command and pcie to sata chip 88SE9170. Signed-off-by: Po Liu <po.liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: ls1021a: Enable CONFIG_OF_LIBFDT and CONFIG_FIT in defconfigAlison Wang2016-05-18-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | In defconfig, enable CONFIG_OF_LIBFDT to support booting DT linux kernel and enable COFNIG_FIT to support FIT image. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie2016-05-18-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-117/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-12-28 18:22:59 +0000