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| * x86: i8042: Reorder static functionsBin Meng2015-08-26-268/+222
| | | | | | | | | | | | | | | | Reorder those static function so that their declarations can be removed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Remove unused codesBin Meng2015-08-26-17/+0
| | | | | | | | | | | | | | Remove unused CONFIG_USE_CPCIDVI wrapped codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Tidy up gpio_ich6_get_base() and callersSimon Glass2015-08-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This function can return an error. Correct the detection of this error so that it works even with large 32-bit addresses. The return value is set up for returning an I/O address but the function is also used to return a memory-mapped address. Adjust the return code to make this work. Also add a bit more debugging. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Correct calls to _ich6_gpio_set_direction()Simon Glass2015-08-26-2/+2
| | | | | | | | | | | | | | These calls seem to be incorrect. The function expects an I/O address but the existing callers pass the value at an I/O address. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: minnowmax: Correct pad-offset value for host_en1Simon Glass2015-08-26-1/+1
| | | | | | | | | | | | | | This should be 0x250, not 0x258. Fix it. Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Add a comment to help find pci_hose_read_config_byte, etc.Simon Glass2015-08-26-0/+1
| | | | | | | | | | | | | | | | These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: minnowmax: Add access to GPIOs E0, E1, E2Simon Glass2015-08-26-0/+27
| | | | | | | | | | | | | | These GPIOs are accessible on the pin header. Add pinctrl settings for them so that we they can be adjusted using the 'gpio' command. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add DSDT table for supporting ACPI on QEMUSaket Sinha2015-08-26-1/+712
| | | | | | | | | | | | | | | | The DSDT table contains a bytecode that is executed by a driver in the kernel. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Tested with QEMU '-M q35' Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add ACPI table support to QEMUSaket Sinha2015-08-26-0/+177
| | | | | | | | | | | | | | | | | | This patch mainly adds ACPI support to QEMU. Verified by booting Linux kernel on QEMU Q35. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Minor whitespace fixes and dropped mention of i440FX in commit message: Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Generate a valid ACPI tableSaket Sinha2015-08-26-0/+855
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement write_acpi_table() to create a minimal working ACPI table. This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT ACPI table entries. Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need actually write the APCI table just like we did for PIRQ routing, MP table and SFI tables. With ACPI table existence, linux kernel gets control of power management, thermal management, configuration management and monitoring in hardware. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tidied up whitespace and aligned some tabs: Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-26-2/+2
| | | | | | | | | | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * fdtdec: Fix possible infinite loop in fdtdec_get_pci_vendev()Bin Meng2015-08-26-2/+1
| | | | | | | | | | | | | | | | When there is no valid compatible string in current list, we should advance to next one in the compatible string list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * patman: use -D option for git format-patchMasahiro Yamada2015-08-26-1/+1
| | | | | | | | | | | | | | | | This allows Patman to generate smaller patches for file removal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-26-5/+40
| | | | | | | | | | | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()Bin Meng2015-08-26-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Remove the fsp_init_phase_pci() callBin Meng2015-08-26-7/+1
| | | | | | | | | | | | | | | | | | It turns out that calling fsp_init_phase_pci() in arch_misc_init() is subject to break pci device drivers as with driver model, when the bus enumeration happens is not deterministic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng2015-08-26-2/+2
| | | | | | | | | | | | | | | | | | | | With dm pci conversion, pci config read/write in unprotect_spi_flash() silently fails as at that time dm pci is not ready and bus enumeration is not done yet. Actually we don't need to do this in that early phase, hence we delay this call to arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Add comments about U-Boot entering start.S twiceBin Meng2015-08-26-4/+6
| | | | | | | | | | | | | | | | | | Add some comments in start.S for the fact that with FSP U-Boot actually enters the code twice. Also change to use fsp_init() and fsp_continue for accuracy. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Enlarge the size of malloc() pool before relocationBin Meng2015-08-26-1/+30
| | | | | | | | | | | | | | | | | | | | After fsp_init() returns, the stack has already been switched to a place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. Enlarge the size of malloc() pool before relocation since we have plenty of memory now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Delay x86_fsp_init() call a little bitBin Meng2015-08-26-3/+3
| | | | | | | | | | | | | | | | Move x86_fsp_init() call after initf_malloc() so that we can fix up the gd->malloc_limit later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Support selected device/driver binding before relocationBin Meng2015-08-26-11/+30
| | | | | | | | | | | | | | | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ifdtool: Drop microcode from the device tree when collatingSimon Glass2015-08-26-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When ifdtool collates the microcode into one place it effectively creates a copy of the 'data' properties in the device tree microcode nodes. This is wasteful since we now have two copies of the microcode in the ROM. To avoid this, remove the microcode data from the device tree and shrink it down. This means that there is only one copy and the overall ROM space used by the microcode does not increase. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ifdtool: Support collating microcode into one placeSimon Glass2015-08-26-10/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel Firmware Support Package (FSP) requires that microcode be provided very early before the device tree can be scanned. We already support adding a pointer to the microcode data in a place where early init code can access. However this just points into the device tree and can only point to a single lot of microcode. For boards which may have different CPU types we must support multiple microcodes and pass all of them to the FSP in one place. Enhance ifdtool to scan all the microcode, place it together in the ROM and update the microcode pointer to point there. This allows us to pass multiple microcode blocks to the FSP using its existing API. Enable the flag in the Makefile so that this feature is used by default for all boards. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ifdtool: Split microcode linking into its own functionSimon Glass2015-08-26-27/+78
| | | | | | | | | | | | | | | | | | | | | | The code to set up the microcode pointer in the ROM shares almost nothing with the write_uboot() function. Move it into its own function so it will be easier to extend. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ifdtool: Check that U-Boot does not overlap other regionsSimon Glass2015-08-26-11/+22
| | | | | | | | | | | | | | | | | | | | Since U-Boot and its device tree can grow we should check that it does not overlap the regions above it. Track the ROM offset that U-Boot reaches and check that other regions (written after U-Boot) do not interfere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Support multiple microcode copiesBin Meng2015-08-26-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Add microcode for BayTrail-I D0 steppingBin Meng2015-08-26-0/+3284
| | | | | | | | | | | | | | | | This commit adds the microcode blob for BayTrail-I D0 stepping, CPUID signature 30679h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Correct microcode documentationSimon Glass2015-08-26-2/+2
| | | | | | | | | | | | | | | | This is incorrect since we require the -m parameter to the microcode tool. Update the two examples to show this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * efi: Update README.efi to clarify build and test instructionsBin Meng2015-08-26-13/+20
| | | | | | | | | | | | | | | | | | The doc has a misleading 'make menuconfig' when building the EFI application and payload. Clarify this and also update information on test with QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Set up video framebuffer for coreboot before loading kernelBin Meng2015-08-26-2/+0
| | | | | | | | | | | | | | | | | | Currenlty we only set up video framebuffer when VIDEO_VESA driver is used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we already saved VESA mode in the VIDEO_COREBOOT driver, now we can also set up video framebuffer for coreboot before loading Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * video: coreboot: Save VESA mode for future useBin Meng2015-08-26-1/+27
| | | | | | | | | | | | | | | | When booting as a coreboot payload, the framebuffer details are passed from coreboot via configuration tables. We save these information into vesa_mode_info structure for future use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boardsBin Meng2015-08-26-4/+1
| | | | | | | | | | | | | | It looks that x86 chipset always contains a host bridge at pci b.d.f 0.0.0, so enable this for all boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Only include cbfs command for corebootBin Meng2015-08-26-0/+2
| | | | | | | | | | | | When running U-Boot bare-metal, the cbfs command is useless. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: kconfig: Hide "System tables" for corebootBin Meng2015-08-26-1/+1
| | | | | | | | | | | | | | When booting as a coreboot payload, we don't need write any configuration tables as coreboot does that for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: kconfig: Hide "System tables" for EFIBin Meng2015-08-26-3/+1
| | | | | | | | | | | | | | Instead of hiding each menu entries under "System tables" for EFI, hide the main menu completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Allow >=4GiB memory bank sizeBin Meng2015-08-26-5/+4
| | | | | | | | | | | | | | Some platforms may have >=4GiB memory, so we need make U-Boot report such configuration correctly when booting as the coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove calculate_relocation_address()Bin Meng2015-08-26-60/+2
| | | | | | | | | | | | | | Now that we have generic routine to calculate relocation address, remove the x86 specific one which is now only used by coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Correctly report E820 typesBin Meng2015-08-26-2/+13
| | | | | | | | | | | | | | coreboot has some extensions (type 6 & 16) to the E820 types. When we detect this, mark it as E820_RESERVED. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Increase memrange entry number to 32Bin Meng2015-08-26-6/+3
| | | | | | | | | | | | | | | | | | Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: doc: Update coreboot payload entry point addressBin Meng2015-08-26-3/+3
| | | | | | | | | | | | | | | | With recent EFI support, the entry point address of coreboot payload was changed. Now we update the address to use _x86boot_start, which is the same one for EFI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * net: e1000: Fix build warnings for 32-bitBin Meng2015-08-26-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6497e37 "net: e1000: Support 64-bit physical address" causes compiler warnings on 32-bit U-Boot build below. drivers/net/e1000.c: In function 'e1000_configure_tx': drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default] drivers/net/e1000.c: In function 'e1000_configure_rx': drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default] This commit fixes the build warnings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-08-26-672/+2448
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| * mtd: nand: mxs invalidate dcache before DMA readPeng Fan2015-08-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | Follow linux dma flow: Before DMA read, be sure to invalidate the cache over the address range of DMA buffer to prevent cache coherency problems. After DMA read, invalidate dcache again. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
| * mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-25-9/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
| * arm: mvebu: Enable NAND on db-mv784mp-gpStefan Roese2015-08-25-0/+6
| | | | | | | | | | | | | | | | | | This patch enables NAND support on the Marvell Armada XP DB-MV784MP-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driverStefan Roese2015-08-25-0/+1693
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cloned from the Linux driver v4.2.0-rc2. Plus some patches from Antoine Tenart enabling controller initialization and ONFI timing support: http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html Please note that this driver needs the Linux NAND subsystem sync to v4.1 from Scott to be applied: https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html Otherwise it will not compile. Tested on the Marvell Armada XP DB-MV784MP-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Scott Wood <scottwood@freescale.com>
| * mtd: nand: Increase max sizes of OOB and Page sizeSiva Durga Prasad Paladugu2015-08-25-3/+3
| | | | | | | | | | | | | | Increase max sizes for OOB, Page size and eccpos to suit for Micron MT29F32G08 part Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * nand: Sync with Linux v4.1Scott Wood2015-08-25-198/+657
| | | | | | | | | | | | | | | | | | | | | | Update the NAND code to match Linux v4.1. The previous sync was from Linux v3.15 in commit 4e67c57125290b25. CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented and not selected by any board. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mtd: Introduce mtd_block_isreserved()Ezequiel Garcia2015-08-25-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to mtd_block_isbad(), which checks if a block is bad or reserved, it's needed to check if a block is reserved only (but not bad). This commit adds an MTD interface for it, in a similar fashion to mtd_block_isbad(). While here, fix mtd_block_isbad() so the out-of-bounds checking is done before the callback check. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> [scottwood: Cherry-picked from Linux 8471bb73ba10ed67] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand: Remove __UBOOT__ ifdefsScott Wood2015-08-25-462/+4
| | | | | | | | | | | | | | I didn't approve the patch that added them. Get them out of the way before doing a sync. Signed-off-by: Scott Wood <scottwood@freescale.com>
generated by cgit v1.1 at 2024-10-09 15:12:58 +0000