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| * | phy: comphy_a3700: Change SD/MMC compatible DT node to match the updatesStefan Roese2017-02-01-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the SD/SDIO/MMC DT properties are updated in the Marvell A3700 and A7/8k DT files, we need to match the checks for compatible node in the PHY driver as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: atmel: rename CONFIG_ATMEL_SDHCI to CONFIG_MMC_SDHCI_ATMELMasahiro Yamada2017-01-31-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_AT91". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: pic32: rename CONFIG_PIC32_SDHCI to CONFIG_MMC_SDHCI_PIC32Masahiro Yamada2017-01-31-9/+9
| | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: msm: rename CONFIG_MSM_SDHCI to CONFIG_MMC_SDHCI_MSMMasahiro Yamada2017-01-31-12/+12
| | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: rockchip: rename CONFIG_ROCKCHIP_SDHCI to CONFIG_MMC_SDHCI_ROCKCHIPMasahiro Yamada2017-01-31-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_ROCKCHIP". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: zynq: rename CONFIG_ZYNQ_SDHCI to CONFIG_MMC_SDHCI_ZYNQMasahiro Yamada2017-01-31-33/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_ZYNQ || ARCH_ZYNQMP". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: sandbox: rename CONFIG, fix dependency, and use it in MakefileMasahiro Yamada2017-01-31-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Rename CONFIG_SANDBOX_MMC to CONFIG_MMC_SANDBOX for consistency I want all MMC driver options prefixed with CONFIG_MMC_. [2] Fix dependency Add necessary depends on to avoid compile error. Instead "depends on MMC" is unneeded because this config entry resides inside of "if MMC". [3] Currently, this config symbol is not referenced at all. Use it to enable/disable the driver in Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: move CONFIG_GENERIC_MMC to KconfigMasahiro Yamada2017-01-31-341/+7
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, CONFIG_GENERIC_MMC seems equivalent to CONFIG_MMC. Let's create an entry for "config GENERIC_MMC" with "default MMC", then convert all macro defines in headers to Kconfig. Almost all of the defines will go away. I see only two exceptions: configs/blanche_defconfig configs/sandbox_noblk_defconfig They define CONFIG_GENERIC_MMC, but not CONFIG_MMC. Something might be wrong with these two boards, so should be checked later. Anyway, this is the output of the moveconfig tool. This commit was created as follows: [1] create a config entry in drivers/mmc/Kconfig [2] tools/moveconfig.py -r HEAD GENERIC_MMC [3] manual clean-up of garbage comments in doc/README.* and include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Prepare v2017.03-rc1Tom Rini2017-01-30-2/+2
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2017-01-29-738/+845
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix clk driver - Optimize DRAM init code for LD20 SoC - Get DRAM information from more reliable source - Clean up SoC init code - Allow to use Image.gz for booting ARM64 Linux - Tidy up environments to use with ATF - Clean up I2C drivers
| * | i2c: uniphier-f: use readl_poll_timeout() to poll registersMasahiro Yamada2017-01-29-24/+10
| | | | | | | | | | | | | | | | | | | | | The readl_poll_timeout() is a useful helper to poll registers and error out if the condition is not met. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | i2c: uniphier(-f): remove unneeded #include <dm/root.h>Masahiro Yamada2017-01-29-2/+0
| | | | | | | | | | | | | | | | | | This include is unnecessary for low-level drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: make update commands more flexible for ATFMasahiro Yamada2017-01-29-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, SPL (u-boot-spl.bin) and U-Boot (u-boot.bin) are stored in non-volatile devices, and some environments are defined to update the images easily. When ARM Trusted Firmware is fully used, SPL is not used. U-Boot proper is contained as BL33 into FIP (Firmware Image Package), which is standard container used by ATF. Allow to use it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: change CONFIG_SPL_PAD_TO to 128KBMasahiro Yamada2017-01-29-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Boot ROM supports authentication feature to prevent malformed software from being run on products. The signature is added at the tail of the second stage loader (= SPL in U-boot terminology). The size of the second stage loader was 64KB, and it was consistent across SoCs. The situation changed when LD20 SoC appeared; it loads 80KB second stage loader, and it is the only exception. Currently, CONFIG_SPL_PAD_TO is set to 64KB and U-Boot proper is loaded from the 64KB offset of non-volatile devices. This means the signature of LD20 SoC (located at 80KB offset) corrupts the U-Boot proper image. Let's move the U-Boot proper image to 128KB offset. It uses 48KB for nothing but padding, and we could actually locate the U-Boot proper at 80KB offset. However, the power of 2 generally seems a better choice for the offset address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: change the offset to environment storage areaMasahiro Yamada2017-01-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When ARM Trusted Firmware is used, bl1.bin + fip.bin exceeds 512KB, so the boot image and the current environment area will overlap. Move the environment storage to 1MB offset. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: set initrd_high environment to skip initrd relocationMasahiro Yamada2017-01-29-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The boot_ramdisk_high() checks the environment "initrd_high" and, if it is set to (ulong)-1, skip the initrd relocation. This is useful for faster booting when we know the initrd is already located within the reach of the kernel. Change "norboot" to copy images in order to make it work without depending on the automatic relocation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: use Image.gz instead Image for booting ARM64 LinuxMasahiro Yamada2017-01-29-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM64 Linux raw image now amounts to 15MB and it is getting bigger and bigger. Using Image.gz saves about 8MB. The cost of unzip is smaller than what we get by saving the kernel loading from non-volatile devices. The ARM32 Linux still uses zImage, a self-decompressor image, so it should not be affected. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: collect SPL CONFIG symbols to the bottom of headerMasahiro Yamada2017-01-29-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | For clarification, move CONFIG symbols that affect SPL building into a single place. Drop #ifdef CONFIG_SPL ... #endif since it is harmless to define CONFIG_SPL_... during U-Boot proper building. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: compile board data only for SPLMasahiro Yamada2017-01-29-1/+1
| | | | | | | | | | | | | | | | | | | | | Now U-Boot proper need not get the uniphier_boards array. Compile it only for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: refactor cmd_ddrmphyMasahiro Yamada2017-01-29-83/+112
| | | | | | | | | | | | | | | | | | Make it look like cmd_ddrphy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: clean up UMC init for PXs2 SoCMasahiro Yamada2017-01-29-283/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | Just cosmetic changes: - Rename prefix DMPHY_ to MPHY_ for consistency - Move UMC parameters below for complete decouple of PHY and UMC - Remove redundant whitespaces Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: refactor cmd_ddrphyMasahiro Yamada2017-01-29-73/+83
| | | | | | | | | | | | | | | | | | | | | It seems more readable to use arrays to get SoC specific parameters instead of the crappy switch statement. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoCMasahiro Yamada2017-01-29-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For LD20 SoC, the last 64 byte of each DRAM bank is used for the dynamic training of DRAM PHY. The regions must be reserved in DT to prevent the kernel from using them. Now gd->bd->bi_dram reflects the actual memory banks. Just use it instead of getting access to the board parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: detect RAM size by decoding HW register instead of DTMasahiro Yamada2017-01-29-50/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot needs to set up available memory area(s) in dram_init() and dram_init_banksize(). It is platform-dependent how to detect the memory banks. Currently, UniPhier adopts the memory banks _alleged_ by DT. This is based on the assumption that users bind a correct DT in their build process. Come to think of it, the DRAM controller has already been set up before U-Boot is entered (because U-Boot runs on DRAM). So, the DRAM controller setup register seems a more reliable source of any information about DRAM stuff. The DRAM banks are initialized by preliminary firmware (SPL, ARM Trusted Firmware BL2, or whatever), so this means the source of the reliability is shifted from Device Tree to such early-stage firmware. However, if the DRAM controller is wrongly configured, the system will crash. If your system is running, the DRAM setup register is very likely to provide the correct DRAM mapping. Decode the SG_MEMCONF register to get the available DRAM banks. The dram_init() and dram_init_banksize() need similar decoding. It would be nice if dram_init_banksize() could reuse the outcome of dram_init(), but global variables are unavailable at this stage because the .bss section is available only after the relocation. As a result, SG_MEMCONF must be checked twice, but a new helper uniphier_memconf_decode() will help to avoid code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoCMasahiro Yamada2017-01-29-175/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB memory footprint, which is significant in SPL. There are PHY parameters for 5 boards, but they are actually not board specific, but SoC specific. After all, we just need to have 2 patterns, for LD20 and LD21. Also, the shift values are small enough to become "short" type instead of "int". This change will save about 3 KB memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clockMasahiro Yamada2017-01-29-3/+3
|/ / | | | | | | | | | | I missed to update them when DT files were resynced with Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | booti: Set images.os.archScott Wood2017-01-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ec6617c39741adc6c549 ("armv8: Support loading 32-bit OS in AArch32 execution state") broke SMP boot by assuming that an image is 32-bit if the arch field in the spin table != IH_ARCH_DEFAULT (i.e. IH_ARCH_ARM64), even if the arch field also does not match IH_ARCH_ARM, even though nothing actually set the arch field in the spin table. Commit e2c18e40b111470f ("armv8: fsl-layerscape: SMP support for loading 32-bit OS") fixed this for bootm by setting the arch field of the spin table based on images.os.arch, but booti remaineed broken because it did not set images.os.arch. Fixes: ec6617c39741adc6c549 ("armv8: Support loading 32-bit OS in AArch32 execution state") Fixes: e2c18e40b111 ("armv8: fsl-layerscape: SMP support for loading 32-bit OS") Cc: Alison Wang <alison.wang@nxp.com> Cc: Chenhui Zhao <chenhui.zhao@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Stuart Yoder <stuart.yoder@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com>
* | fs/fat: Fix unaligned __u16 reads for FAT12 accessStefan Brüns2017-01-28-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Doing unaligned reads is not supported on all architectures, use byte sized reads of the little endian buffer. Rename off16 to off8, as it reflects the buffer offset in byte granularity (offset is in entry, i.e. 12 bit, granularity). Fix a regression introduced in 8d48c92b45aea91e2a2be90f2ed93677e85526f1 Reported-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Tested-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
* | buildman: Update link to the most recent prebuilt ARC toolachinAlexey Brodkin2017-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | To troubleshoot unexpected bhavior during building and what's more important during execution it is strongly recommended to use recent ARC toolchain, and so we're now referring to arc-2016.09 which is the latest as of today. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: SPI: stm32: add stm32f746 qspi driverMichael Kurz2017-01-28-2/+712
| | | | | | | | | | | | This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
* | ARM: stm32: enable support for smsc phy on stm32f746-disco boardMichael Kurz2017-01-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | This patch enables support for the smsc phy on the stm32f746-disco board. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> Series-changes 3: - Add Acked-by tag to 'enable support for smsc phy on...'
* | net: phy: add SMSC LAN8742 phyMichael Kurz2017-01-28-0/+12
| | | | | | | | | | | | | | This patch adds support for SMSC LAN8742 in phylib Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: stm32: add designware mac glue code for stm32Michael Kurz2017-01-28-3/+122
| | | | | | | | | | | | | | | | This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: stm32: use clock setup function defined in clock.cMichael Kurz2017-01-28-30/+15
| | | | | | | | | | | | | | | | | | | | | | Use the clock setup function defined in clock.c instead of setting the clock bits directly in the drivers. Remove register definitions of RCC in rcc.h as these are already defined in the struct in stm32.h Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: stm32: fix stm32f7 sdram fmc base addressMichael Kurz2017-01-28-3/+2
| | | | | | | | | | | | | | | | | | The fmc base address is defined twice, once in fmc.h and once in stm32.h. Fix wrong definition in stm32.h. Remove the definiton in fmc.h. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: stm32: cleanup stm32f7 filesMichael Kurz2017-01-28-124/+111
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - use rcc struct instead of macro additions Add missing stm32f7 register in rcc struct Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA<vikas.manocha@st.com>
* | ARM: DTS: stm32: add stm32f746-disco device tree filesMichael Kurz2017-01-28-0/+242
| | | | | | | | | | | | | | | | | | | | | | This patch adds the DTS source files needed for stm32f746-disco board The files are based on the stm32f429/469 files from current linux kernel. Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi" Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* | ARM: DTS: stm32: add stm32f746 device tree pin control filesMichael Kurz2017-01-28-0/+1324
| | | | | | | | | | | | | | | | | | This patch adds pin control definitions for use in device tree files The definitions are based on the stm32f746 files from current linux kernel "include/dt-bindings/pinctrl/stm32f746-pinfunc.h". Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* | arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703Adam Ford2017-01-28-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but anything else is lumped into 36XX/37XX with an assumed 1GHz speed. Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ). This also adds the ability to distinguish between the DM3730, DM3725, AM3715, and AM3703 and correctly display their maximum speed. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
* | arm: omap3: Fix cpuinfo frequency spellingLadislav Michl2017-01-28-3/+3
| | | | | | | | | | | | Frequency is measured in Hz. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* | Revert "armv8: release slave cores from CPU_RELEASE_ADDR"Masahiro Yamada2017-01-28-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8c36e99f211104fd7dcbf0669a35a47ce5e154f5. There is misunderstanding in commit 8c36e99f2111 ("armv8: release slave cores from CPU_RELEASE_ADDR"). How to bring the slave cores into U-Boot proper is platform-specific. So, it should be cared in SoC/board files instead of common/spl/spl.c. As you see SPL is the acronym of Secondary Program Loader, there is generally something that runs before SPL (the First one is usually Boot ROM). How to wake up slave cores from the Boot ROM is really SoC specific. So, the intention for the spin table support is to bring the slave cores into U-Boot proper in an SoC specific manner. (this must be done after relocation. see below.) If you bring the slaves into SPL, it is SoC own code responsibility to transfer them to U-Boot proper. The Spin Table defines the interface between a boot-loader and Linux kernel. It is unrelated to the interface between SPL and U-Boot proper. One more thing is missing in the commit; spl_image->entry_point points to the entry address of U-Boot *before* relocation. U-Boot relocates itself between board_init_f() and board_init_r(). This means the master CPU sees the different copy of the spin code than the slave CPUs enter. The spin_table_update_dt() protects the code *after* relocation. As a result, the slave CPUs spin in unprotected code, which leads to unstable behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm64: spin-table: add more information in Kconfig helpMasahiro Yamada2017-01-28-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature seems to be sometimes misunderstood. The intention is: [1] Bring the slaves into the U-Boot proper image, not SPL (unless you have a special reason to do otherwise). [2] The operation must be done in a board (SoC) specific manner since how to wake the slaves from the Boot ROM is SoC specific. [3] The slaves must enter U-Boot proper after U-Boot relocates itself because the "cpu-release-addr" property points to the relocated memory area. [2] is already explained in the help. We can make [1] even clearer by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing, so I am adding it to the list. Instead, "before the master CPU jumps to the kernel" is a matter of course, so removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | board/chiliboard: Add support for chiliBoardMarcin Niestroj2017-01-28-0/+532
| | | | | | | | | | | | | | | | | | | | | | | | | | chiliBoard is a development board which uses chiliSOM as its base. Hardware specification: * chiliSOM (TI AM335x, DRAM, NAND) * Ethernet PHY (id 0) * USB host (usb1) * MicroSD slot (mmc0) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: am335x: Add support for chiliSOMMarcin Niestroj2017-01-28-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * TI AM335x processor * 128M, 256M or 512M DDR3 memory * up to 256M NAND We place source inside arch/arm/mach-omap2/ directory and make it possible to reuse initialization code (i.e. DDR, NAND init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | defconfig: Add a config for AM335x High Security EVMAndrew F. Davis2017-01-28-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new defconfig file for the AM335x High Security EVM. This config is specific for the case of memory device booting. Memory device booting is handled separatly from peripheral booting on HS devices as the load address changes. This defconfig is the same as for the non-secure part, except for: CONFIG_TI_SECURE_DEVICE option set to 'y' CONFIG_ISW_ENTRY_ADDR updated for secure images. CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_USE_TINY_PRINTF option set to 'y' to reduce SPL size CONFIG_SPL_SYS_MALLOC_SIMPLE set to 'y' to reduce SPL size Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | spl: Remove overwrite of relocated malloc limitAndrew F. Davis2017-01-28-1/+6
| | | | | | | | | | | | | | | | | | | | | | spl_init on some boards is called after stack and heap relocation, on some platforms spl_relocate_stack_gd is called to handle setting the limit to its value CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN when simple SPL malloc is enabled during relocation. spl_init should then not re-assign the old pre-relocation limit when this is defined. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | malloc_simple: Add debug statements to memalign_simpleAndrew F. Davis2017-01-28-1/+5
| | | | | | | | | | | | | | Add debug statements to memalign_simple to match malloc_simple. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | aspeed: Support for ast2500 Eval Boardmaxims@google.com2017-01-28-0/+94
| | | | | | | | | | ast2500 Eval Board device tree and board specific configuration. Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Board init functions and common configs for ast2500 based boardsmaxims@google.com2017-01-28-1/+165
| | | | | | | | | | | | | | | | Add configuration file with parameters that are very likely to be shared by all ast2500-based boards. Add ast2500-board.c file with the init code that is very likely to be shared by all ast2500-based boards. Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+1273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-07 23:36:58 +0000