summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* malta: enable HUSH parserPaul Burton2015-01-29-0/+1
| | | | | | | | The malta board is used for development and thus the shell is interacted with often. Enable HUSH to make the experience a little more pleasant. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* malta: delay after resetPaul Burton2015-01-29-0/+1
| | | | | | | | Reset isn't instant, so delay to give it a chance. Otherwise we go on to print a failure message before resetting anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* malta: IDE supportPaul Burton2015-01-29-0/+35
| | | | | | | | | This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: clear TagLo select 2 during cache initPaul Burton2015-01-29-2/+8
| | | | | | | | | | Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: allow systems to skip loads during cache initPaul Burton2015-01-29-6/+19
| | | | | | | | | | | | | Current MIPS systems do not require that loads be performed to force the parity of cache lines, a simple invalidate by clearing the tag for each line will suffice. Thus this patch makes the loads & subsequent second invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD option, and defines that for existing mips32 targets. Exceptions are malta where this is known to be unnecessary, and qemu-mips where caches are not implemented. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: inline mips_init_[id]cache functionsPaul Burton2015-01-29-58/+28
| | | | | | | | | | | The mips_init_[id]cache functions are small & only called once from a single callsite. Inlining them allows mips_cache_reset to avoid having to bother moving arguments around & leaves it a leaf function which is thus able to simply keep the return address live in the ra register throughout, simplifying the code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: refactor cache loops to a macroPaul Burton2015-01-29-17/+13
| | | | | | | | Reduce duplication by performing loops through cache tags using an assembler macro. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: refactor L1 cache config reads to a macroPaul Burton2015-01-29-56/+41
| | | | | | | | | Reduce duplication between reading the configuration of the L1 dcache & icache by performing both using a macro which calculates the appropriate line & cache sizes from the coprocessor 0 Config1 register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify cache initialization codePaul Burton2015-01-29-224/+15
| | | | | | | | | | | | | | The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move the more developed mips32 version to a common arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in order to reduce duplication. The temporary registers used are shuffled slightly in order to work for both mips32 & mips64 builds. The RA register is defined differently to suit mips32 & mips64, but will be removed by a later commit in the series after further cleanup. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify cache maintenance functionsPaul Burton2015-01-29-167/+119
| | | | | | | | | Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: avoid .set ISA for cache operationsPaul Burton2015-01-29-38/+33
| | | | | | | | | | | | As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set <ISA>" directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-01-26-288/+1078
|\
| * x86: config: chromebook_link: Enable environmentSimon Glass2015-01-24-0/+7
| | | | | | | | | | | | | | Enable an environment area. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-24-28/+0
| | | | | | | | | | | | This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-24-0/+6
| | | | | | | | | | | | | | Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+464
| | | | | | | | | | | | | | | | | | | | | | The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add SPI flash MRC details for chromebook_linkSimon Glass2015-01-24-1/+14
| | | | | | | | | | | | | | | | Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Allow architecture-specific memory reservationSimon Glass2015-01-24-0/+7
| | | | | | | | | | | | | | All memory to be reserved for use after relocation by adding a new call to perform this reservation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: spi: Add device tree supportSimon Glass2015-01-24-0/+8
| | | | | | | | | | | | | | As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: rtc: mc146818: Add helpers to read/write CMOS RAMSimon Glass2015-01-24-48/+105
| | | | | | | | | | | | | | On x86 we use CMOS RAM to read and write some settings. Add basic support for this, including access to registers 128-255. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Use ipchecksum from net/Simon Glass2015-01-24-97/+4
| | | | | | | | | | | | | | The existing IP checksum function is only accessible to the 'coreboot' cpu. Drop it in favour of the new code in the network subsystem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: Add a separate file for IP checksummingSimon Glass2015-01-23-0/+91
| | | | | | | | | | | | | | | | Move the checksum code out into its own file so it can be used elsewhere. Also use a new version which supports a length which is not a multiple of 2 and add a new function to add two checksums. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add compatible string for Intel ICH9 SPI controllerSimon Glass2015-01-23-0/+2
| | | | | | | | | | | | | | Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: tegra: Fix port information parsingSjoerd Simons2015-01-23-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the new fdtdec pci helpers. To get the device index of the root port, the "reg" property should be parsed from the dtb (as was previously the case). With this patch i can successfully network boot my jetson tk1 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * x86: Fix various code format issues in start16.SBin Meng2015-01-23-10/+10
| | | | | | | | | | | | | | | | | | | | | | Various minor code format issues are fixed in start16.S: - U-boot -> U-Boot - 32bit -> 32-bit - Use TAB instead of SPACE to indent - Move the indention location of the GDT comment block Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-23-2/+19
| | | | | | | | | | | | | | | | | | | | On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Save mtrr support flag in global dataBin Meng2015-01-23-6/+14
| | | | | | | | | | | | | | | | CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.cBin Meng2015-01-23-0/+2
| | | | | | | | | | | | | | | | arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: config: Always scroll the display by 5 lines, for speedSimon Glass2015-01-23-0/+1
| | | | | | | | | | | | | | | | Scrolling a line at a time is very slow for reasons that I don't understand. It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope with this, scroll 5 lines each time. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: video: Add support for CONFIG_CONSOLE_SCROLL_LINESSimon Glass2015-01-23-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time. This same option is available for LCDs so when these systems are unified this code can be unified also. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * x86: Access the VGA ROM when neededSimon Glass2015-01-23-2/+42
| | | | | | | | | | | | | | Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Fix out of bounds irq handlers accessSebastien Ronsse2015-01-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using coreboot-x86_defconfig, the following error occurred prior to this modification: CC arch/x86/lib/interrupts arch/x86/lib/interrupts.c: In function ‘do_irqinfo’: arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations] if (irq_handlers[irq].handler != NULL) { ^ arch/x86/lib/interrupts.c:133:2: note: containing loop for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { ^ cc1: all warnings being treated as errors scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed make[1]: *** [arch/x86/lib/interrupts.o] Error 1 Makefile:1093: recipe for target 'arch/x86/lib' failed make: *** [arch/x86/lib] Error 2 Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e Signed-off-by: Sebastien Ronsse <sronsse@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ahci: Make sure interface is not busy after enabling the portBin Meng2015-01-23-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each time U-Boot boots on Intel Crown Bay board, the displayed hard drive information is wrong. It could be either wrong capacity or just a 'Capacity: not available' message. After enabling the debug switch, we can see the scsi inquiry command did not execute successfully. However, doing a 'scsi scan' in the U-Boot shell does not expose this issue. SCSI: Target spinup took 0 ms. SATA link 1 timeout. AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8 Type: Hard Disk Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512) Found 1 device(s). So uninitialized contents on the stack were passed to dev_print() to display those wrong information. The symptom were observed on two hard drives (one is Seagate, the other one is Western Digital). The fix is to make sure the AHCI interface is not busy by checking the error and status information from task file register after enabling the port in ahci_port_start() before proceeding other operations like scsi_scan(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: Drop the x86_fb driverSimon Glass2015-01-23-49/+1
| | | | | | | | | | | | | | | | Now that we have a full VESA driver we may as well use that. We need to support the VESA layer being set up by early start-up code or by running a VGA ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add a VESA video driverSimon Glass2015-01-23-0/+75
| | | | | | | | | | | | | | | | | | Add a driver intended to cope with any VESA-compatible x86 graphics adapter. It will not support ROMs which use OpenFirmware (Forth) since there is no support for that in U-Boot. This means that MAC OS cards will not work. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: pci: Don't stop when we get a vendor/device mismatchSimon Glass2015-01-23-1/+1
| | | | | | | | | | | | | | These are quite common and we may as well press on and not be so picky. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * bios_emulator: Add some VESA interface debuggingSimon Glass2015-01-23-22/+148
| | | | | | | | | | | | Allow the supported modes to be listed when in debug mode. Signed-off-by: Simon Glass <sjg@chromium.org>
| * bios_emulator: Don't display error when emulator terminatesSimon Glass2015-01-23-1/+1
| | | | | | | | | | | | As it turns out this is a normal condition, so suppress the error. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Support ROMs on other archsSimon Glass2015-01-23-1/+8
| | | | | | | | | | | | | | | | We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Correct endianness isues in pci_romSimon Glass2015-01-23-11/+14
| | | | | | | | | | | | | | | | This code is too x86-dependent at present. Correct it so that it can run on big-endian machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * bios_emulator: Fix an #ifdef typo in the header fileSimon Glass2015-01-23-1/+1
| | | | | | | | | | | | | | This stops the debug mode from working properly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-21/+109
|\ \
| * | ARM: atmel: sama5d4_xplained: enable usb ethernet gadgetBo Shen2015-01-19-0/+8
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4_xplained: add option for usb ethernet gadgetBo Shen2015-01-19-0/+11
| | | | | | | | | | | | | | | | | | | | | Add the option for USB Ethernet gadget based on atmel usb device. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4ek: enable usb ethernet gadgetBo Shen2015-01-19-0/+8
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4ek: add option for usb ethernet gadgetBo Shen2015-01-19-0/+11
| | | | | | | | | | | | | | | | | | | | | Add the option for USB Ethernet gadget based on atmel usb device. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add usb platform dataBo Shen2015-01-19-1/+1
| | | | | | | | | | | | | | | | | | The SAMA5D4 has the same usb platform data with SAMA5D3 SoC. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | arm: at91: snapper9260: Drop invalid CONFIG_SKIP_RELOCATE_UBOOTSimon Glass2015-01-19-1/+0
| | | | | | | | | | | | | | | | | | This config is not valid, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | ARM: at91: sama5d3_xplained: spl: enable PMECC header generationWu, Josh2015-01-19-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As sama5d3 xplained support the PMECC. So add the PMECC header for spl binary. That make ROM loader can use PMECC to avoid error flips in spl code in nandflash. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com>
generated by cgit v1.1 at 2024-09-17 18:11:20 +0000