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* sh: place board lowlevel_init code in the beginning of .textVladimir Zapolskiy2016-12-02-19/+19
| | | | | | | | | Reference lowlevel_init of all supported SH2A/SH3/SH4/SH4A boards from a shared linker script, the lowlevel_init function will be called by a relative address. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: use single u-boot linker script for all boardsVladimir Zapolskiy2016-12-02-253/+7
| | | | | | | | | | | | | | Three supported SH4/SH4A boards with the bootloader image stored on SPI flash have own flavour of a linker script, in turn they are equal among each other. The only difference is that the text from lowlevel_init.o is placed right after start.o, which makes sense. Note that .bss section is not marked as NOLOAD, because for about 10 years this is a default option of a GNU linker, either the attribute is found or not the resulting image file is the same. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: sh: add necessary define bits to board_fVladimir Zapolskiy2016-12-02-6/+9
| | | | | | | | | | Since a platform conversion to generic board support has not been accomplished some architecture specific bits are missing from board_f init sequence, the change adds a number of basic expected callbacks into early init sequence. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* r2dplus: select rtl8139 driver in defconfigVladimir Zapolskiy2016-12-02-0/+2
| | | | | | | | | | | | | | CONFIG_RTL8139 was moved to a board defconfig by a commit 86e9dc86b1a2 ("net: Move CONFIG_RTL8139 to Kconfig"), however it was done incorrectly due to a missing CONFIG_NETDEVICES selection, thus virtually it was just a removal of the driver compilation. As an unlucky consequence the option was completely removed by a purge commit adad96e60d0e ("configs: Re-sync HUSH options"), restore the driver inclusion back. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* r2dplus: use P1 area space for text base and PCI system memoryVladimir Zapolskiy2016-12-02-5/+5
| | | | | | | | | | | | | While both options are acceptable use P1 area physical addresses instead of external memory space of text base and PCI system memory for unification purposes, all other supported superh boards have the same selection. This allows to easily ensure that CONFIG_SYS_TEXT_BASE is located within available DRAM. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: remove __io config options from r2dplus and r7780mp boardsVladimir Zapolskiy2016-12-02-12/+0
| | | | | | | | Defined __io is no-op for the SH architecture and it can be removed from board files without any functional change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: sh7751: map PCI memory space into SDRAMVladimir Zapolskiy2016-12-02-6/+4
| | | | | | | | | | | | | For ease of use and accounting a condition that on SH4 pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to unimplemented __iomem() conversion, this change fixes access to SDRAM memory by PCI devices. This change also generalizes PCI system memory configuration, which is taken from board specific defines rather than hardcoded in the PCI host driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* pci: sh7751: fix up PCI I/O space addressVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | The change actually maps PCI I/O window to the same address on PCI bus as it is stated by a comment, before the change transfers to the PCI I/O space are failed due to misconfiguration of the most significant 14 bits of the PCI address in PCIIOBR (note that it is set to 0x0). Most probably the problem remained unnoticed, because communcation to all tested PCI devices is done over PCI memory space only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* sh4: cache: move exported cache manipulation functions into cache.cVladimir Zapolskiy2016-12-02-39/+36
| | | | | | | | | No functional change, moving cache manipulation functions into cache.c allows to collect all of them in a single location and as a pleasant side effect cache_control() function can be unexported now. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: cache: don't modify CCR from P1 areaVladimir Zapolskiy2016-12-02-5/+3
| | | | | | | | | | | cache_wback_all() is a local function and it is called from cache_control() only, which is in turn jumps to P2 area. The change fixes an issue when cache_wback_all() returns from P2 to P1, however cache_control() continues to manipulate with CCR register, according to the User's Manual this is restricted. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* sh: cache use jump_to_P2() and back_to_P1() from asm/system.hVladimir Zapolskiy2016-12-02-37/+2
| | | | | | | | Both jump_to_P2() and back_to_P1() functions are found in asm/system.h header file and functionally they are the same, don't redefine them. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh3: remove unused cache.c file from being builtVladimir Zapolskiy2016-12-02-97/+1
| | | | | | | | | | | | | The change is similar to commit 994b56616bae ("sh: delete an unused source file") for SH2, however here the removed cache.c file was built and included into an image as a dead code. If it is needed in future the contents can be reused from a similar arch/sh/cpu/sh4/cache.c file, which is in turn will be moved to a shared among all core flavours location at arch/sh/lib/cache.c. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: cache: correct flush_cache() to writeback and invalidateVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | In common usecases flush_cache() assumes both cache invalidation and write-back to memory, instead of doing cache invalidation only with the wrapped 'ocbi' instruction pin flush_cache() to cache invalidation with memory write-back done by 'ocbp'. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: cache: correct dcache flush to invalidate with write-backVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | In common usecases flush_cache() assumes both cache invalidation and write-back to memory, thus in flush_dcache_range() implementation change SH4 cache write-back only instruction 'ocbwb' with cache purge instruction 'ocbp', according to the User's Manual there should be no performance penalty for that. Note that under circumstances only cache invalidation is expected from flush_cache() call, in these occasional cases the current version of flush_cache() works, which is a wrapper over invalidate_dcache_range() at the moment, this will be fixed in the following change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* compiler.h: use u-boot endian macros on OpenBSDJonathan Gray2016-12-02-14/+4
| | | | | | | | | | | | | When building u-boot on sparc64 and powerpc hosts it became clear that u-boot expects endian conversion defines to be macros: lib/crc32.c:87: error: braced-group within expression allowed only inside a function For OpenBSD switch from using system definitions equivalent to the u-boot ones and define glibc __BYTE_ORDER __BIG_ENDIAN __LITTLE_ENDIAN names, as at least some parts of the non-cross build assumes those names are present (ie crc32.c). Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
* ARM: am57xx_evm: enable DFU supportSekhar Nori2016-12-02-0/+14
| | | | | | | | | | | | | | | | | AM57xx GP EVM has USB2 port of the SoC exposed as USB client port. It is useful to be able to use this port for USB DFU downloads. Enable USB DFU support. Tested on AM57x GP EVM Rev A3 using DFU to download to connected SD card. configs for HS version of the AM57x EVM are included in the patch but not really tested. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: ti: consolidate dfu environment variablesSekhar Nori2016-12-02-148/+82
| | | | | | | | | | | | Introduce include/environment/ti/dfu.h that consolidates environment variable definitions for various TI boards that support DFU today. Tested on AM335x EVM, AM437x SK EVM and DRA74x EVM by using DFU to write to SD card. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* cmd: scsi: Make private functions staticMichal Simek2016-12-02-2/+2
| | | | | | | | | | Two functions should be static because they are not exported to any other file. Warnings were reported by sparse C=1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Separate SCSI private block description initializationMichal Simek2016-12-02-6/+22
| | | | | | | | | | When blk_create_device() is called some parameters in blk_desc are automatically filled. Separate SCSI private initialization and SCSI full block device initialization not to rewrite already prepared data. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Change scsi_scan() to be able to return valueMichal Simek2016-12-02-6/+13
| | | | | | | | | | With DM_SCSI this function will return more than one return value to cover errors. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Make private functions staticMichal Simek2016-12-02-6/+10
| | | | | | | | | | Several functions should be static because they are not exported to any other file. Warnings were reported by sparse C=1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Remove completely unused functionsMichal Simek2016-12-02-38/+0
| | | | | | | | | | These functions are not called for any location. This patch removes them scsi_trim_trail(), scsi_get_disk_count() and scsi_setup_read6(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Simplify scsi_read/scsi_write()Michal Simek2016-12-02-16/+11
| | | | | | | | | | There is no reason to directly point to static allocated array when we have proper block_dev pointer available via parameter in !CONFIG_BLK. For CONFIG_BLK this is read directly from uclass platdata. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Move pccb buffer initalization directly to scsi_detect_devMichal Simek2016-12-02-6/+6
| | | | | | | | pccb is pointer to temporary buffer which is used only for sending command. Make it local as is done in scsi_read/scsi_write. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Take lun from device block descriptionMichal Simek2016-12-02-6/+5
| | | | | | | | Prepare LUN(Logical unit number) directly in block description structure and reuse it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Extract device detection algorithmMichal Simek2016-12-02-61/+82
| | | | | | | | The patch enables running detection algorithm on block device description structure. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Extract block device initializationMichal Simek2016-12-02-20/+25
| | | | | | | Extract block device initialization to specific function. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: miiphyutil: Work and report phy address in hex in mdio cmdMichal Simek2016-12-02-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is confusing that mdio commands work and report phy id as decimal value when mii is working with hex values. For example: ZynqMP> mdio list gem: 21 - TI DP83867 <--> ethernet@ff0e0000 ZynqMP> mdio read ethernet@ff0e0000 0 Reading from bus gem PHY at address 21: 0 - 0x1140 ZynqMP> mii dump 21 0 Incorrect PHY address. Range should be 0-31 ... ZynqMP> mii dump 15 0. (1140) -- PHY control register -- (8000:0000) 0.15 = 0 reset U-Boot normally takes hex values that's why this patch is changing mdio command to handle hex instead of changing mii command to handle decimal values. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* ARM: zynq: Enable SD1 and qspi for picozed boardSiva Durga Prasad Paladugu2016-12-02-0/+12
| | | | | | | Enable SD1 and qspi for picozed board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq(mp): remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT definesMasahiro Yamada2016-12-02-2/+0
| | | | | | | | | | ARCH_ZYNQ(MP) selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT is not used. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: List secondary software boot modesMichal Simek2016-12-02-0/+15
| | | | | | | | Using alternative bootmode field to support automatic secondary boot modes. It is purely software setting where SW modes are using free bootmode combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Use DTS name for different psu_init_gpl* files in SPLMichal Simek2016-12-02-1/+1
| | | | | | | | | | | | | | | CONFIG_SYS_CONFIG_NAME is not proper config option for different low level init files because different board revisions requires different psu_init_gpl* files. Also at the end of moving drivers to DM all board specific configuration files should be removed. The same changes was done for Zynq. "ARM: zynq: Simplify zynq configuration" (sha1: ad5b5801264e573bfbf17a20b04c546985c5bfc1) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-12-02-1/+1
| | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-01-5/+62
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| * tools/kwbimage: add DEBUG optionChris Packham2016-12-01-1/+10
| | | | | | | | | | | | | | | | | | Offset 0x1 in the generated kwb image file is a set of flags, bit 0 enables debug output from the BootROM firmware. Allow a DEBUG option in the kwb configuration to request debug output from the BootROM firmware. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * tools/kwbimage: add BAUDRATE optionChris Packham2016-12-01-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | Offset 0x18 in some Marvell datasheets this field is redacted as "reserved". This offset is actually a set of options and bits 2:0 allow the selection of the UART baudrate. Allow a BAUDRATE option to set the UART baudrate for any messages coming from the BootROM firmware. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: move SYS_MVEBU_PLL_CLOCK to KconfigChris Packham2016-12-01-3/+6
| | | | | | | | | | | | | | | | | | | | The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mvebu: db-88f6820-amc: Enable FIT supportChris Packham2016-12-01-0/+2
| | | | | | | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | SPL: mmc: Make spl_mmc_load_image availableMarek Vasut2016-12-01-2/+5
| | | | | | | | | | | | | | | | | | | | Make the spl_mmc_load_image() available globally, so it can be invoked directly by SPL on extremely space-constrained systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: Tinification of the mmc codeMarek Vasut2016-12-01-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | Add new configuration option CONFIG_MMC_TINY which strips away all memory allocation within the MMC code and code for handling multiple cards. This allows extremely space-constrained SPL code use the MMC framework. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: Fix warning if debug() is not usedMarek Vasut2016-12-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If debug() is not used, then the whole content of debug(...) will be removed by the preprocessor, which will result in the following warning. This patch adds __maybe_unused annotation to fix this. drivers/mmc/mmc.c: In function ‘mmc_init’: drivers/mmc/mmc.c:1685:11: warning: variable ‘start’ set but not used [-Wunused-but-set-variable] unsigned start; Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: add bkops-enable commandTomas Melin2016-12-01-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | Add new command that provides possibility to enable the background operations handshake functionality (BKOPS_EN, EXT_CSD byte [163]) on eMMC devices. This is an optional feature of eMMCs, the setting is write-once. The command must be explicitly taken into use with CONFIG_CMD_BKOPS_ENABLE. Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
* | mmc: s5p_sdhci: fix to check proper pinmux idSeung-Woo Kim2016-12-01-1/+1
|/ | | | | | | At sdhci_get_config(), there was wrong condition to check pimux id, so this patch fixes to check proper pinmux id. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
* ts4600: Disable CONFIG_DISPLAY_CPUINFOTom Rini2016-11-30-0/+1
| | | | | | | | | | | | Without this change we see: ../arch/arm/cpu/arm926ejs/mxs/mxs.c: In function ‘print_cpuinfo’: ../arch/arm/cpu/arm926ejs/mxs/mxs.c:181:23: warning: unused variable ‘data’ [-Wunused-variable] ../arch/arm/cpu/arm926ejs/mxs/mxs.c:180:6: warning: variable ‘cpurev’ set but not used [-Wunused-but-set-variable] So the easy solution is to disable CONFIG_DISPLAY_CPUINFO Reviewed-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-11-30-65/+584
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| * MIPS: Fix map_physmem for cached mappingsPaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips: Let cache.h be included from assembly sourceMarek Vasut2016-11-30-0/+2
| | | | | | | | | | | | | | | | | | Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * common/board_f: enable initr_trap for MIPSDaniel Schwierzeck2016-11-30-2/+2
| | | | | | | | | | | | | | | | Enable initr_trap hook also for MIPS to install and enable U-Boot's specific MIPS exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck2016-11-30-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
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