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* mmc: sd: optimize erasePeng Fan2016-10-18-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | To SD, there is no erase group, then the value erase_grp_size will be default 1. When erasing SD blocks, the blocks will be erased one by one, which is time consuming. We use AU_SIZE as a group to speed up the erasing. Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB. `time mmc erase 0x100000 0x2000` time: 44.856 seconds (before optimization) time: 0.335 seconds (after optimization) Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com> (cherry picked from commit e492dbb41e025ac1a7d7934b1df52b2f0485f8dd)
* mmc: sd: extracting erase related information from sd statusPeng Fan2016-10-18-0/+77
| | | | | | | | | | | | | | | | | Add function to read SD_STATUS information. According to the information, get erase_timeout/erase_size/erase_offset. Add a structure sd_ssr to include the erase related information. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com> (cherry picked from commit 3697e5992f89c923aca17d7d9174739da28cb3cd)
* MLK-13336 mx6sll_arm2: Update LPDDR2 script to v2.1Ye Li2016-10-13-3/+10
| | | | | | | | | | | | | | | | | | | | Changes: Version 2.1 -Issue a Precharge-All command prior to the MRW Reset command. setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results setmem /32 0x021B0848 = 0x3A383C40 // [MMDC_MPRDDLCTL] setmem /32 0x021B0850 = 0x242C3020 // [MMDC_MPWRDLCTL] File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Passed overnight memtester on one i.MX6SLL LPDDR2 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13335 mx6sl: Fix build break for all i.MX6SL boardsYe Li2016-10-13-2/+2
| | | | | | | | Since the UART1 register base name is changed from UART1_IPS_BASE_ADDR to UART1_BASE to align with other i.MX6 chips. Should update the board configuration header file with the new name. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13331 mx6sll_arm2: Output WDOG_B signal to reset PMICYe Li2016-10-12-0/+8
| | | | | | | Since the LPDDR2/3 does not have reset pin, to keep safe reset, we need to use WDOG_B to reset PMIC. Add pinmux and relevant settings. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13330 mx6sll_arm2: Update LPDDR3 script to v2.2Ye Li2016-10-12-7/+14
| | | | | | | | | | | | | | | | | | | | | | | Changes from v1.2 to v2.2: Version 2.2 -Issue a Precharge-All command prior to the MRW Reset command. -setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 -setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 Version 2.1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results -setmem /32 0x021B0848 = 0x3C3A3C3C // [MMDC_MPRDDLCTL] -setmem /32 0x021B0850 = 0x24293625 // [MMDC_MPWRDLCTL] Version 1.2.1 -Fix a typo. setmem /32 0x020E052C = 0x00000030 -Fix a typo. setmem /32 0x021B0800 = 0xA1390003 File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Overnight memtester passed on two i.MX6SLL LPDDR3 ARM2 boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13311 configs: mx6sll_lpddr3_arm2: Enable network functionPeter Chen2016-10-11-0/+5
| | | | | | | Since mx6sll has no ethernet controller, we take USB ethernet device as network device by default. Signed-off-by: Peter Chen <peter.chen@nxp.com>
* MLK-13307-15 imx: mx6sll: add mx6sll arm2 supportPeng Fan2016-10-11-0/+1352
| | | | | | | | | | | Add mx6sll lpddr3/lpddr2 arm2 support. LCDIF/SPI/USB/PMIC supported. LPDDR3 DDR version: 1.2 LPDDR2 DDR version: initial version. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-14 imx-common: lcdif: update lcdif regs for i.MX6SLLPeng Fan2016-10-11-4/+5
| | | | | | | Update lcdif regs for i.MX6SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-13 OCOTP: Update OCOTP driver to support i.MX6SLLYe Li2016-10-11-8/+10
| | | | | | | | The i.MX6SLL reuses the i.MX6ULL fuse, and has same fuse bank map. Add the i.MX6SLL support to OCOTP driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2016-10-11-6/+71
| | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-11 imx: mx6sll: disable LDOPeng Fan2016-10-11-0/+2
| | | | | | There is no LDO for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-10 mx6_common: correct loadaddr and text base for i.MX6SLLPeng Fan2016-10-11-1/+1
| | | | | | Correct loadaddr and text base for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-9 imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-10-11-0/+4
| | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-8 imx-common: cache: configure L2 Cache for i.MX6SLLPeng Fan2016-10-11-1/+1
| | | | | | Configure L2 Cache for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2016-10-11-5/+16
| | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-6 imx: mx6sll: add clock support for i.MX6SLLPeng Fan2016-10-11-36/+158
| | | | | | | Update clock settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-5 imx: mx6sll: add iomux settingsPeng Fan2016-10-11-4/+10
| | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-4 imx-common: timer: add i.MX6SLL supportPeng Fan2016-10-11-2/+4
| | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-3 imx: mx6sll: update register addressPeng Fan2016-10-11-41/+52
| | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-2 imx: mx6sll: add pinmux header filesPeng Fan2016-10-11-0/+1021
| | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-1 imx: Add MX6SLL CPU typePeng Fan2016-10-11-1/+4
| | | | | | | Add i.MX6SLL CPU type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mx6: clock: Fix the logic for reading axi_alt_selFabio Estevam2016-09-18-2/+2
| | | | | | | | | | | | | | According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> (cherry picked from commit 8f2e2f15ffa1bb03b6e6e189312426059f3215d1)
* MLK-13131: mx6qarm2: add fastboot and recovery supportAdrian Alonso2016-09-13-0/+33
| | | | | | Add fastboot and recovery mode support for mx6qarm Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13130: configs: mx6qarm2: android lpddr2 pop supportAdrian Alonso2016-09-13-1/+94
| | | | | | Add Android support for mx6qarm2 lpddr2 pop target Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividersAdrian Alonso2016-09-07-1/+1
| | | | | | | | Adjust ahb/axi clock root podf dividers to be divided by 1 to allow ahb/axi clock root to be 24Mhz when sourced from osc_clk. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* Disable MMU and Cache when using pluginUtkarsh Gupta2016-09-01-0/+28
| | | | Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
* MLK-13141 mx6qpsabresd: Do not touch VGEN3 and VGEN5Robin Gong2016-08-30-12/+14
| | | | | | | | VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board, so software didn't need to change their voltage output anymore. Otherwise, VGEN3 will be wrongly updated from 1.8v to 2.8v. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-13140 ARM: imx: update REFTOP_VBGADJ according to fuse settingBai Ping2016-08-30-5/+0
| | | | | | | | | | | | | | | | On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13124 ARM: imx: update the REFTOP_VBGADJ settingBai Ping2016-08-25-6/+32
| | | | | | | | | | | | | | | | | Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13115 imx: mx6ullevk: Update LPDDR2 script for i.MX6ULL 9x9 EVKYe Li2016-08-23-4/+4
| | | | | | | | | | | | | | | | | | Update the LPDDR2 script to 1.2 rev with delay line settings changed. File: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx Changes: Update Delay Line Settings based on the delay line calibration results of more boards. MMDC_MPRDDLCTL = 0x40403439 MMDC_MPWRDLCTL = 0X4040342D Test: One 9x9 EVK board pass stress memtester. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13070 imx: mx6ullevk: Add 9x9 EVK supportYe Li2016-08-12-21/+27
| | | | | | | | | | | | | | | | Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script for the board to version 1.0. DDR script: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.inc Changes: Initial version Test: Passed memtester overnight test on 1 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12929 imx6ull: support splash screen for epdcRobby Cai2016-07-29-1/+322
| | | | | | | add splash screen feature for epdc. it's tested on imx6ull arm2 board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATAYe Li2016-07-29-4/+14
| | | | | | | | | | | | | | We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before this changing, SATA read/write can't work after it. And we have to re-init SATA. The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing. This patch is an work around that moves the ENET clock setting (enable_fec_anatop_clock) from ethernet init to board_init which is prior than SATA initialization. So there is no PLL6 change after SATA init. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12998 imx: mx6ullevk: Add build targets for boot devicesYe Li2016-07-26-0/+15
| | | | | | Add build targets for eMMC, NAND and QSPI NOR. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12964 imx: enlarge mux width to 4Peng Fan2016-07-22-8/+7
| | | | | | For i.MX6, the mux width is 4, not 3. So enlarge the width. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12988 imx: mx6ull Add board support for i.MX6ULL EVKYe Li2016-07-19-0/+2088
| | | | | | | | | | | | | | | | | | | | | Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok to work. The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when it is needed. The DDR3 script is using version 1.2: File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc Test: 3 boards passed memtester. Build target: mx6ull_14x14_evk_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12985 imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-07-15-0/+5
| | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Ye.Li <ye.li@nxp.com>
* dfu: avoid memory leakPeng Fan2016-07-01-1/+3
| | | | | | | | | | | | | | | | When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> (cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)
* MLK-12894 imx6ull: adjust the ldo 1.2v bandgap voltage on i.mx6ullBai Ping2016-06-08-0/+7
| | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-12889 mx6ullarm2: Update DDR script to version 2.2Ye Li2016-06-08-2/+2
| | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.inc Changes: Change MMDC_MDMISC.WALAT to 1 setmem /32 0x021B0018 = 0x00211740 Test: Passed memtester on two mx6ull ddr3 arm2 boards Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12888 usb: ehci: only shutdown opened controllerPeng Fan2016-06-06-0/+4
| | | | | | | | | | | | | | | | If the usb controller is not running, no need to shutdown it, otherwise `usb stop` complains about: "EHCI failed to shut down host controller". To i.MX7D SDB, there are two usb ports, one Host, one OTG. If we only plug one udisk to the Host port and then `usb start`, the OTG controller for OTG port does not run actually. Then, if `usb stop`, the OTG controller for OTG port will also be shutdown, but it is not running. This patch adds a check that only shutdown the running controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12883 usb: limit USB_MAX_XFER_BLK to 256Peng Fan2016-06-06-1/+3
| | | | | | | | | | | | | | | | | | | For Some USB mass storage devices, such as: " - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA - Class: (from Interface) Mass Storage - PacketSize: 64 Configurations: 1 - Vendor: 0x0930 Product 0x6545 Version 1.16 " When `usb read 0x80000000 0 0x2000`, we met "EHCI timed out on TD - token=0x80008d80". The devices does not support scsi VPD page, we are not able to get the maximum transfer length for READ(10)/WRITE(10). So we limit this to 256 blocks as READ(6). Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output settingYe Li2016-06-06-1/+1
| | | | | | | | | LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
* MLK-12852 ocotp: mxc: mx6ull: fix GP3/GP4 progPeng Fan2016-06-03-1/+7
| | | | | | | | | | | | Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word' is not correct when program bank 8, since ocotp controller actully use word index. For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67. But actully it should be (7 << 3 | 7) ---> 63. So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12865 Nand: Fix BCH debug1 register access issueYe Li2016-05-31-1/+1
| | | | | | Should have "&" to access the register address, otherwise uboot will hang. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12848: mx6ull_14x14_ddr3_arm2: add new TSC configHaibo Chen2016-05-24-0/+21
| | | | | | | | Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2 board, disable PMIC and ldo bypass check. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-12845 imx: mx6sabre_common: fix mmcargsPeng Fan2016-05-23-2/+2
| | | | | | | A space should be added after ${smp}. If not, bootargs is wrong, when CONFIG_SYS_NOSMP defined. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK boardHan Xu2016-05-23-0/+9
| | | | | | | | add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when NAND enabled due to pin conflict. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
* MLK-12798 imx6ull: fix snvs tamper pin usagePeng Fan2016-05-16-16/+30
| | | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable using these pins. Signed-off-by: Peng Fan <peng.fan@nxp.com>
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