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* MLK-12800 imx: mx7dsabresd: support revCPeng Fan2016-05-16-4/+13
| | | | | | Add revC board support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLLYe Li2016-05-16-0/+10
| | | | | | | | | | | | In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12775 mx6ullarm2: Add package size info to the build target and dtb fileYe Li2016-05-11-1/+1
| | | | | | | | To align with i.MX6UL, add the chip package size info to the i.MX6ULL ARM2 board build target and loading dtb file name. So that mfgtool and yocto can follow i.MX6UL naming rule to process i.MX6ULL. Signed-off-by: Ye Li <ye.li@nxp.com>
* imx: iomux-v3: fix UART input selectsStefan Agner2016-05-10-4/+4
| | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2. From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2016-05-09-24/+34
| | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12766 net: fec: do not access reserved register for i.MX6ULLPeng Fan2016-05-09-1/+1
| | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6ULL. Accessing these register will cause enet not work well or cause system report fault. Reported-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flowAnson Huang2016-05-09-1/+13
| | | | | | | | | | | | On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. For LPSR mode, ddr resume flow is same as retention mode, just adjust it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention modeAnson Huang2016-05-09-3/+3
| | | | | | | | i.MX7D TO1.2 removes the DDR PADs retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-1 imx: adjust i.mx7d standby voltage settingAnson Huang2016-05-09-14/+14
| | | | | | | i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12693-2 nand: mxs: correct bitflip for erased NAND pagePeng Fan2016-05-07-2/+22
| | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12693-1 nand: mxs: fix the bitflips for erased page when uncorrectable errorPeng Fan2016-05-06-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is porting from linux: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768 " We may meet the bitflips in reading an erased page(contains all 0xFF), this may causes the UBIFS corrupt, please see the log from Elie: ----------------------------------------------------------------- [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes ... [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815 [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383 [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383 ----------------------------------------------------------------- This patch does a check for the uncorrectable failure in the following steps: [0] set the threshold. The threshold is set based on the truth: "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH do the ECC." For the sake of safe, we will set the threshold with half the gf_len, and do not make it bigger the ECC strength. [1] count the bitflips of the current ECC chunk, assume it is N. [2] if the (N <= threshold) is true, we continue to read out the page with ECC disabled. and we count the bitflips again, assume it is N2. (We read out the whole page, not just a chunk, this makes the check more strictly, and make the code more simple.) [3] if the (N2 <= threshold) is true again, we can regard this is a erased page. This is because a real erased page is full of 0xFF(maybe also has several bitflips), while a page contains the 0xFF data will definitely has many bitflips in the ECC parity areas. [4] if the [3] fails, we can regard this is a page filled with the '0xFF' data. " Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-06-1/+1
| | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
* MLK-12723 imx: Change the env offset on NAND to 60MYe Li2016-05-06-8/+8
| | | | | | | | | | | | | | | Current environment offset on NAND is 37MB, this will cause a alignment issue when erasing if nand erase block is 2MB. The saveenv is failed. => saveenv Saving Environment to NAND... Erasing NAND... Attempt to erase non block-aligned data Since the max erase block we supported is 4MB, adjust the env offset to 60MB, where is the last 4MB in 64MB reserved area for boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12629-2: i.MX6QP: update pluginPeng Fan2016-05-04-0/+12
| | | | | | For i.MX6QP, the QoS settings is different from others. Align with DCD. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12629-1: imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-04-3/+6
| | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled, chaning value of ACR will cause SLVERR, uboot hangs. In some cases, such as plugin, L2 Cache enabled bit is not cleared, then "Set bit 22 in the auxiliary control register" cause uboot hangs. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12739: imx: tools: imximage: fix CLR bit commandAdrian Alonso2016-05-03-1/+1
| | | | | | | | Fix incorrect parametr in CMD_CHECK_BITS_CLR command Pass CLR parameter to DCD header for CMD_CHECK_BITS_CLR Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12737 mx6qp/mx6dp: Fix runtime CPU type checking issueYe Li2016-05-03-9/+33
| | | | | | | | | | | 2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When doing runtime cpu type checking, we can't use CPU type of i.MX6Q and i.MX6D for them more, which is ok in 2015 u-boot. This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to do the checking. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12736 mx6ulevk: Delete obsoleted android build targetYe Li2016-04-29-14/+0
| | | | | | | The build target mx6ul_14x14_evk_android_defconfig is obsoleted. It is replaced by mx6ul_14x14_evk_brillo_defconfig. So remove this old file. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2016-04-29-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
* MLK-12705-2 imx7d: add build target for TO1.1Anson Huang2016-04-29-6/+6
| | | | | | | Default build target supports TO1.0 and TO1.2, TO1.1 uses its own defconfig. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2Anson Huang2016-04-29-59/+59
| | | | | | | | i.MX7D TO1.2 uses same DDR script as TO1.0, TO1.1 uses dedicated DDR script. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)
* MLK-12711 imx: correct speed grading info for i.MX6ULPeng Fan2016-04-28-0/+15
| | | | | | Correct speed grading info for i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12694 mx6ullarm2: Remove the CD detection of SD2Ye Li2016-04-22-3/+1
| | | | | | | | | | Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause SD2 access problem even the card is inserted. Hard code the CD result to 1 to assume the card is always on. The SD driver will return other errors if the card does not exist. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)
* MLK-12691-2 mx6ullarm2: Add build targets for various boot devicesYe Li2016-04-21-0/+20
| | | | | | Four build targets added for eMMC, NAND, QSPIA and SPINOR boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12691-1 mx6ullarm2: Update config file to remove unnecessary settingsYe Li2016-04-21-6/+3
| | | | | | | To align with other i.mx6 platforms, update config file to remove some unnecessary settings. Also enable the GPIO command. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devicesYe Li2016-04-21-8/+11
| | | | | | | | | | | | | | | 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
* MLK-12690 imx: mx6ull: fix build error for pluginPeng Fan2016-04-21-1/+1
| | | | | | | | | Fix build error for Plugin "Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor" Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 95860f1213c038ef2e5900d1874ff5398ac0be2a)
* MLK-12677 mx6ullarm2: Update DDR script to version 2.1Ye Li2016-04-20-5/+6
| | | | | | | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)
* MLK-12658 imx: adjust POR_B setting on i.MX6ULLAnson Huang2016-04-15-0/+14
| | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12603: mtd: gpmi: may use legacy bch geometry in u-bootHan Xu2016-04-13-0/+6
| | | | | | | | | | provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy bch geometry. NOTICE: the feature must be enabled/disabled in both u-boot and kernel. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 0abc9c182c24f88522bd74fa1b53cd2fa3477184)
* MLK-12616-11 imx: mx6ull: add mx6ull arm2 board supportPeng Fan2016-04-13-0/+1204
| | | | | | | | | | | | | Support mx6ull ddr3 arm2 board. DDR script version 1.1. Passed memtester on 3 boards. Take mx6ul 14x14 ddr3 arm2 as reference. Note: LCD/NAND/ECSPI not tested, need hardware rework. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 584050b98cf070bb608b652e89659ff20c47efba)
* MLK-12616-10 mx6ull: Add AIPS3 initializationYe Li2016-04-13-2/+3
| | | | | | | Since the mx6ull adds the AIPS3, so enable its initialization. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f774a4c12b8ef197483075bbcd840b3ea27308e9)
* MLK-12616-9 mx6ull: Update memory map addressYe Li2016-04-13-2/+18
| | | | | | | | Update memory map address for mx6ull which uses AIPS3 and adjust UART8 to AIPS3 by replacing for ESAI. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5154e0c15965019602a7c128abe00d58b6e26ff1)
* MLK-12616-8 mx6ull: update CCM registers and clock settingsYe Li2016-04-13-20/+79
| | | | | | | Update CCM registers and clock settings according the mx6ull changes Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 60cb811a0e9abbdd89e498c499fa4e63a18fae58)
* MLK-12616-7 mx6ull: Not setting ahb clockPeng Fan2016-04-13-1/+1
| | | | | | Rom already initialized clock at 396M and 132M for arm core and ahb Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12616-6 mx6ull: Update s_init to skip pfd resetYe Li2016-04-13-1/+2
| | | | | | | | The PFD reset is not needed for mx6ull, since it uses runtime cpu id checking here, add codes to skip it. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 4543971c6078410078efbc830b9fc86363e7bebd)
* MLK-12616-5 GPT: Update GPT driver for MX6ULLYe Li2016-04-13-3/+4
| | | | | | | | The MX6ULL has GPT with supporting OSC clock source, update the driver accordingly. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b2740fd7a0f8d80b416d4de1f57b6542407d23bd)
* MLK-12616-4 OCOTP: Update driver for mx6ullPeng Fan2016-04-13-6/+39
| | | | | | | | | | The MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other banks use 256 bits. So we have to adjust the word and bank index when accessing the bank 8. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit bb71569f51762cdee876fc4a6154624285d548f5)
* MLK-12616-3 mx6ull: Enable CONFIG_MX6UL definition for MX6ULLYe Li2016-04-13-0/+4
| | | | | | | | | | Since iMX6ULL is derivative of iMX6UL, most of design are same, so enable CONFIG_MX6UL to reduce duplicated effort. We can use CONFIG_MX6ULL for the difference between these two chips. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b3b0a429ef66d334e776052c1a9a281aeb568e05)
* MLK-12616-2 mx6ull: add MX6ULL major CPU TypeYe Li2016-04-13-2/+5
| | | | | | | Add MXC_CPU_MX6ULL for i.MX6ULL CPU ID Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7377004dfc8d5d01f6ca7899f6355a0ac4ea7f8a)
* MLK-12616-1 mx6ull: Add iomux header fileYe Li2016-04-13-0/+1065
| | | | | | | Add iomux headers according the file SDK_IOMaps_i.MX6ULL_Headers_b151218.zip Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a78b5b07bd8f15f6c896d85289174e7ed0fc76c1)
* MLK-12591: Define MX6UL_SNVS_LP_BASE_ADDR to avoid build breakPeng Fan2016-03-28-2/+3
| | | | | | | | | We have runtime checking now, since SNVS_LP_BASE_ADDR is only for i.MX6UL now, so it will break building for other i.MX6[x]. Introduce MX6UL_SNVS_LP_BASE_ADDR to avoid build break. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12576 imx: imx6ul: disable POR_B internal pull upAnson Huang2016-03-25-7/+18
| | | | | | | | | | From TO1.1, SNVS adds internal pull up control for POR_B, the register filed is GPBIT[1:0], after system boot up, it can be set to 2b'01 to disable internal pull up. It can save about 30uA power in SNVS mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 5fd1cb94781926dca4bfdc2804f2550dcd6b65a5)
* MLK-12575-2 imx: Modify environment offset to 6 sectors on EIMNORYe Li2016-03-25-4/+4
| | | | | | | | | | On mx6qsabreauto and mx6sx ARM2 boards, the EIMNOR sector size is 128KB. And its u-boot environment offset is 4 sectors (512KB). But u-boot size has exceeds it, so change to 6 sectors offset (768KB). To align the environment configurations for all i.MX, also change the configuration for mx6ul and mx7d, which has EIMNOR with 256KB sectors. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12575-1 imx: Modify environment offset to 768K for SD/MMC/eMMCYe Li2016-03-25-11/+11
| | | | | | | | Since the u-boot size has exceeded the 512KB on some platforms, so we set the environment offset to 768KB for all i.MX6 and i.MX7 reference boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12416-11: support saveenv for sataPeng Fan2016-03-25-4/+175
| | | | | | Support saveenv for sata. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12296 imx: mx7dsabresd: Change default env for M4 boot to TCMYe Li2016-03-25-1/+5
| | | | | | | | | | | | Since the QSPI needs to rework on this board, at default the QSPI is disabled. So bind the M4 QSPI boot with QSPI enabled u-boot image, set default M4 boot to TCM. Need to use TCM m4 image at default. Additional, on SDB there is only one QSPI flash. Considering the A7 QSPI boot case, we have to move M4 image to 1M offset to give enough space for u-boot and env. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-10186-1 imximage: add fixed IVT offset supportYe.Li2016-03-25-1/+8
| | | | | | | | | | Since from mx7, we use fixed IVT offset for all boot devices. Introduce a new configuration CONFIG_IMX_FIXED_IVT_OFFSET for this. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 88e0a3552b08627b18d98380a32dbafacb18854b) (cherry picked from commit 3d52e221ed444dab96038a2417d1dcb2217ad593)
* MLK-12565 mx7: rdc: Change IS_ENABLED to remove build warningYe Li2016-03-25-2/+3
| | | | | | | Change to use #ifdef not the IS_ENABLED, because we will get build warning when the CONFIG_IMX_RDC is not set. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12416-10: mx6ul: Add comments for BEEPeng Fan2016-03-25-0/+3
| | | | | | Add comments for enabling BEE. Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-12-23 14:58:26 +0000