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* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-45/+66
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| * arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-10/+19
| | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * mx6sabre_common: Use the default CONFIG_SYS_PBSIZEFabio Estevam2014-12-01-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * config_fallbacks: Add a default entry for CONFIG_SYS_PBSIZEFabio Estevam2014-12-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the characters of the error message: "Unknown command '' - try 'help'". Provide a default size for CONFIG_SYS_PBSIZE so that it can store the error message and allows the error message to be printed correctly with no hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * tbs2910: fix lost characters on serial inputSoeren Moch2014-12-01-1/+1
| | | | | | | | | | | | | | | | | | With enabled console_mux for serial input and usb keyboard sometimes characters get lost when typing too fast at the serial input (pasting strings in serial console window). Fix this by using INT_QUEUE for polling the usb keyboard. Signed-off-by: Soeren Moch <smoch@web.de>
| * arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * sata: fix reset_sata for dwc_ahsataSoeren Moch2014-12-01-6/+11
| | | | | | | | | | | | | | | | | | | | | | - fix crash when sata device is not initialized - remove disable_sata_clock() since it is not clear which clock for which device should be disabled here - call disable_sata_clock() for mx6 in preboot_os instead Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * tbs2910: fix KconfigSoeren Moch2014-12-01-8/+1
| | | | | | | | | | | | fix Kconfig for tbs2910 board to prevent crash on relocation Signed-off-by: Soeren Moch <smoch@web.de>
| * mxc_ocotp: Do not disable the OCOTP clock after every accessFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leave the OCOTP turned on, so that we subsequent access do not fail. After enabling the thermal driver on a mx6sxsabresd board: U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 48 C Reset cause: POR Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller In: serial Out: serial Err: serial Net: (hang) As the thermal driver accesses the ocotp registers, its clock will be disabled afterwards. Then when the MAC address is read (also from ocotp registers) it will cause a hang. Do not disable the ocotp clock to prevent this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
| * mx6sxsabresd: Add thermal supportFabio Estevam2014-12-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add thermal support so that the temperature of the chip can be displayed on boot: U-Boot 2015.01-rc1-18268-g1366c05-dirty (Nov 25 2014 - 13:02:42) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 50 C Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * thermal: imx_thermal: Do not display calibration dataFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Printing the calibration data on every boot does not provide really useful information: U-Boot 2015.01-rc1-18266-ge7eb277 (Nov 24 2014 - 11:29:51) CPU: Freescale i.MX6Q rev1.2 at 792 MHz CPU: Thermal calibration data: 0x5d85067d CPU: Temperature 33 C Reset cause: POR Board: MX6-SabreSD Do not display the calibration data in order to have a cleaner boot log. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mxs_ocotp: clear the error flag before initiating write operationHector Palacios2014-12-01-0/+2
| | | | | | | | | | | | | | A previous operation may have set the error flag, which must be cleared before a new write operation can be issued. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * mxs_ocotp: check for errors from the OTP controller after writingHector Palacios2014-12-01-0/+7
| | | | | | | | | | | | | | | | | | The write operation may fail when trying to write to a locked area. In this case the ERROR bit is set in the CTRL register. Check for that condition and return an error. Signed-off-by: Hector Palacios <hector.palacios@digi.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mxs_ocotp: prevent error path from returning successHector Palacios2014-12-01-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code may goto 'fail' upon error with 'ret' variable set to an error code, but this variable was being overwritten by a final preparation function to restore the HCLK, so success was (in general) returned even after an error was hit previously. With this change, the function may now return success even if the final preparation function fails, but it's probably enough to print a message because (if successful) the real programming of the fuses has already completed. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * imx: mx53loco: Add raw initrd supportGuillaume GARDET2014-12-01-0/+1
| | | | | | | | | | | | | | Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Acked-by: Jason Liu <r64343@freescale.com>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2014-12-10-103/+391
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| * | arm: rmobile: alt: Add support MMC and MMC commandNobuhiro Iwamatsu2014-12-10-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | Alt board has been connected to eMMC of 8GB to MMC port. This enables MMC port and MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Add support MMC and MMC commandNobuhiro Iwamatsu2014-12-10-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Lager board has been connected to eMMC of 8GB to MMC1 port. This enables MMC1 port and MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Add support ext2 and ext4 file systemNobuhiro Iwamatsu2014-12-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Board with R-Car SoC has USB and MMC. They might use the EXT2 or EXT4 file system. This adds support ext2 and ext4 file system Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add mmc.h for sh_mmcif of rmobileNobuhiro Iwamatsu2014-12-10-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver. This adds arch-rmobile/mmc.h that defines mmcif_mmc_init(). Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Stop clock prior to booting kernelNobuhiro Iwamatsu2014-12-05-3/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | This stops clock except INTC-RT, MSIF, INTC-SYS, IRQC and SCIF before kernel boots. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Add structure for infomation of module control registerNobuhiro Iwamatsu2014-12-05-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The infomation of module control register for R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are almost the same, they can be combined into one structure. This provides structure that summarizes infomation of module control register and default register values. And this structure is the module control use of the kernel at boot time. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Add infomation of bits for module control registerNobuhiro Iwamatsu2014-12-05-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds infomation of bits for module control register. This is used to control modules on ARM R-Car SoCs. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Add mstp_setclrbits and mstp_setclrbits_le32Nobuhiro Iwamatsu2014-12-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This addes macro for set and clear bit control for module control register. This is used when user want to disable the function of the devices corresponding to register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Move arch_preboot_os function to rcar-gen2-common/common.cNobuhiro Iwamatsu2014-12-05-32/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arch_preboot_os function used in boards using R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) is common. This makes rcar-gen2-common/common.c file providing common function for R-Car ARM SoC, and moves this function to this file. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Move control macro of mstp to arch-rmobile/rcar-mstp.hNobuhiro Iwamatsu2014-12-05-36/+26
| | | | | | | | | | | | | | | | | | | | | | | | Control macro of mstp is common in R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794). This moves these to arch-rmobile/rcar-mstp.h Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: rcar: Move module control register to header file of SoCNobuhiro Iwamatsu2014-12-05-35/+39
| | | | | | | | | | | | | | | | | | | | | | | | Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are same address. This moves these to header file of SoC. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | dm: stv0991: Move serial to driver modelVikas Manocha2014-12-09-5/+25
| | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | stv0991: increase the initial ram size configVikas Manocha2014-12-09-1/+1
| | | | | | | | | | | | | | | | | | It is done to make space available for driver model memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | stv0991: enable default and misc command configsVikas Manocha2014-12-09-2/+19
| | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | stv0991: enable ethernet supportVikas Manocha2014-12-09-1/+151
| | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | stv0991: Add basic stv0991 architecture supportVikas Manocha2014-12-09-0/+764
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add arch/arm/cpu/armv7/Makefile hunk] Signed-off-by: Tom Rini <trini@ti.com>
* | | Prepare v2015.01-rc3Tom Rini2014-12-08-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-08-144/+6835
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| * | | powerpc/hydra: fix judging condition of RGMII selectionMinghuan Lian2014-12-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains selection bits and connected status bit. So the Corresponding mux value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/hydra: Update MDIO mux fixupsChunhe Lan2014-12-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new device trees use a more generic interface for supporting muxing mdio buses. The mux property is thus specified in "reg", rather than "fsl,hydra-mdio-muxval". In order to support using old device trees, we keep the old fixup in there. Linux will therefore see the both properties, but will ignore fsl,hydra-mdio-muxval. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t4240rdb: enable eSDHC 3.3V supportXiaobo Xie2014-12-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SD supply Voltage was 3.3V on T4240RDB, so enabled 3.3V support for eSDHC. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Wujie Qiu <B49553@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: use correct dma compatible for several SoCsTudor Laurentiu2014-12-05-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer qoriq socs have an updated dma ip block with a different compatible. Let's make sure we use the proper string so that the dmas get their liodn. In order to have the means to specify the compatible string, the liodn setting macros were updated to receive a new parameter for it. The following SoCs were changed to use the new compatible: T1023/4, T1040, T2080/1, T4240, B4860. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | board/t1024qds: add retimer support on t1024qdsShengzhou Liu2014-12-05-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize retimer for XFI on t1024qds. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | t1024qds: increase IO drive strengthShengzhou Liu2014-12-05-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | net/phy: enable serdes auto-negotiation for vsc8514 phyShengzhou Liu2014-12-05-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VSC8514 QSGMII PHY requires enabling auto-negotiation, otherwise it wouldn't work. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | board/t1024qds: update pin multiplexingShengzhou Liu2014-12-05-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add multiplexing support among SPI flash, TDM riser card and SDXC. it routes SPI pins to SPI flash by default. Route SPI pins to SD slot if "adaptor=sdxc" is set in hwconfig. Route SPI pins to TDM riser card and do fixup for dts if "pin_mux=tdm" is set in hwconfig. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | net/fman: update 10GEC to fit new SoCShengzhou Liu2014-12-05-2/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t1024rdb: Add T1024 RDB board supportShengzhou Liu2014-12-05-0/+2093
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t1024qds: Add T1024 QDS board supportShengzhou Liu2014-12-05-0/+2700
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1024QDS is a high-performance computing evaluation, development and test platform for T1024 QorIQ Power Architecture processor. T1024QDS board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Three 1G/2.5Gbps SGMII ports - Four 1Gbps QSGMII ports - one 10Gbps XFI or 10Base-KR interface - SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora - PCIe: Three PCI Express controllers with five PCIe slots. - IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - Video: DIU supports video up to 1280x1024x32 bpp. - Chrontel CH7201 for HDMI connection. - TI DS90C387R for direct LCD connection. - Raw (not encoded) video connector for testing or other encoders. - QUICC Engine block - 32-bit RISC controller for flexible support of the communications peripherals - Serial DMA channel for receive and transmit on all serial channels - Two universal communication controllers, supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - eSPI: Three SPI flash devices. - SATA: one SATA 2.O. - USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC. - I2C: Four I2C controllers. - UART: Two UART on board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Add T1024/T1023 SoC supportShengzhou Liu2014-12-05-2/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Add workaround for faulty SPDYork Sun2014-12-05-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Update LIODN entries for T1040Priyanka Jain2014-12-05-7/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t2080: updating rcw for silicon v1.1Shengzhou Liu2014-12-05-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0, and also update core frequency to 1.8GHz for v1.1. We reserve the support for T2080 v1.0 and enable v1.1 by default. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfigSuresh Gupta2014-12-05-2/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp respectively in hwconfig. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-12-26 18:57:29 +0000