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* spi: ti_qspi: Fix baudrate divider calculationVignesh R2016-11-13-9/+7
| | | | | | | | | Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* ARM: dts: dra7xx: Update spi-max-frequency for qspi slave nodeVignesh R2016-11-13-2/+2
| | | | | | | | | Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: k2g: Update PLL Multiplier and divider valuesLokesh Vutla2016-11-13-1/+1
| | | | | | | | | | | Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18 [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: PLL: Enable glitch free initialization sequenceLokesh Vutla2016-11-13-8/+8
| | | | | | | | | | Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy2016-11-13-1/+6
| | | | | | | | | | | | | | | | | While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: print the cache config option in hex instead of decimalKeerthy2016-11-13-1/+1
| | | | | | | Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mx6ull_14x14_evk: Add README fileDiego Dorta2016-11-13-0/+36
| | | | | | | | | Add a README file to help users getting started with the board. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* davinci: omapl138_lcdk: keep booting even when MAC address is invalidFabien Parent2016-11-13-6/+8
| | | | | | | | | | | | If the MAC address specified on the EEPROM is invalid (multicast or zero address), then u-boot fails to boot. Having a bad MAC address in the EEPROM should not prevent the system from booting. This commit changes the error path to just print an error messages in case of bad MAC address. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: am335x/mux: Do not hang when encountering a bad EEPROMAlex G2016-11-13-2/+2
| | | | | | | | | | | | | | | | | | | | | In most cases, the SPL and u-boot.img will be on the same boot media. Since the SPL was loaded by the boot rom, the pinmux will already have been configured for this media. This, the board will still be able to boot successfully, or at least reach the u-boot console, where more recovery options are available. I've encountered this on a beaglebone black with a corrupted EEPROM. Removing this check allowed the board to boot successfully. I've also seen this on EVM-based boards with an unprogrammed EEPROM. On those boards, for some reason there were no UART messages. This made it look as if the SOC was dead. Remove the hang(), as it is not a fatal error. Also reformat the error message to be clearer as to the cause. The original message made it appear as if the wrong binary was being loaded. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* igep00x0: add Hynix timingsLadislav Michl2016-11-13-4/+16
| | | | | | | | | Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and Hynix H27S4G6F2DKA-BM Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Javier Martinez Canillas <javier@samsung.com> Tested-by: Javier Martinez Canillas <javier@samsung.com>
* igep00x0: consolidate defconfigsLadislav Michl2016-11-13-36/+5
| | | | | | | | Defconfigs should remain the same except CONFIG_SYS_EXTRA_OPTIONS. Drop NAND specific defconfig as flash type is runtime detected. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Javier Martinez Canillas <javier@samsung.com>
* igep00x0: disable CONFIG_DISPLAY_BOARDINFOLadislav Michl2016-11-13-18/+3
| | | | | | | | | | | As a single U-Boot binary can now run on various board modifications, drop CONFIG_DISPLAY_BOARDINFO as it prints flash memory information too early to give us chance to easily detect it. Also saves few bytes as a bonus. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Javier Martinez Canillas <javier@samsung.com> Tested-by: Javier Martinez Canillas <javier@samsung.com>
* tools: fix mksunxiboot build for tools-all targetAndre Przywara2016-11-13-1/+1
| | | | | | | | | | | | Commit fed329aebe3a ("tools: add mksunxiboot to tools-all target") added mksunxiboot to the tools-all target, but used the CONFIG_SUNXI symbol to enable its build. Now commit aec9a0f19f64 ("sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXI"), merged before that, renamed that symbol, so that the first patch basically gets ineffective. Adjust the symbol name in tools/Makefile to make it build again. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-11-08-32/+69
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| * ARM: tegra186: call secure monitor for all cache-wide opsStephen Warren2016-11-07-3/+21
| | | | | | | | | | | | | | | | | | An SMC call is required for all cache-wide operations on Tegra186. This patch implements the two missing hooks now that U-Boot supports them, and fixes the mapping of "hook name" to SMC call code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * armv8: add hooks for all cache-wide operationsStephen Warren2016-11-07-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: translate __asm_flush_l3_cache to assemblyStephen Warren2016-11-07-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When performing a cache disable function, code must not access DRAM. That is because when the cache is disabled, it will be bypassed and all loads and stores will be serviced by RAM. This prevents accessing any dirty data in the cache. In turn, this means the stack cannot be used, since that is in RAM. To guarantee that code doesn't use RAM (and in particular the stack) __asm_flush_l3_cache() must be manually implemented in assembly, rather than implemented in C since the compiler won't know not to touch RAM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: ensure nvtboot_boot_x0 alignmentStephen Warren2016-11-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned. So far this has happened by accident! Fix the code so this is guaranteed. This fixes the following build error: ... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol `nvtboot_boot_x0' ... Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-11-07-24/+1849
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| * | net: use random ethernet address if invalid and not zeroSiva Durga Prasad Paladugu2016-11-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use random ethernet address if the ethernet address found is invalid, not zero and config for random address is defined. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvgbe: Fix build error with CONFIG_PHYLIBChris Packham2016-11-07-22/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5a49f17481bb ("net: mii: Use spatch to update miiphy_register") updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to satisfy the phylib APIs. Because these functions weren't updated in that commit build errors where triggered when CONFIG_PHYLIB was enabled. Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write and using smi_reg_read/smi_reg_write directly. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: center FLP burst timing at 16msAsh Charles2016-11-07-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms specified by the IEEE802.3 standard from the chip's default of 8ms. For more details, see the "Auto-Negotiation Timing" section of the KSZ9031RNX datasheet. [1] https://patchwork.kernel.org/patch/6558371/ Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: tegra: enable Ethernet on p2771-0000Stephen Warren2016-11-07-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the Ethernet device in DT, provide board-specific configuration, and enable the driver in Kconfig. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DTStephen Warren2016-11-07-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the Tegra186 SoC DT so that boards can make use of it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: tegra: configure Ethernet address on Tegra186Stephen Warren2016-11-07-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, the bootloader which runs before U-Boot passes the Ethernet MAC address to U-Boot using device tree. Extract this value and write it to the environment, so that the Ethernet uclass picks it up and uses it for the built-in Ethernet device. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: tegra: add SoC-level hook for board_late_init()Stephen Warren2016-11-07-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the Tegra186 implementation of board_late_init() to call a per-SoC "hook" function. This will allow SoC-specific (rather than Tegra-wide) functionality to be implemented without the core Tegra code needing to be aware of the details. While board186.c is currently only used for Tegra186, it should be applicable to any other future SoC, and perhaps its simple design could be back-ported to older SoCs in the future too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: add driver for Synopsys Ethernet QoS deviceStephen Warren2016-11-07-0/+1564
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports the Synopsys Designware Ethernet QoS (Quality of Service) a/k/a eqos IP block, which is a different design than the HW supported by the existing designware.c driver. The IP supports many options for bus type, clocking/reset structure, and feature list. This driver currently supports the specific configuration used in NVIDIA's Tegra186 chip, but should be extensible to other combinations quite easily, as explained in the source. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> # V1 Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | dt: net: add DWC EQoS bindingStephen Warren2016-11-07-0/+166
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which supports multiple options for bus type, clocking and reset structure, and feature list. This patch imports the binding from the Linux kernel, including my V3 patch to extend the binding to cover the Tegra186, which is applied for next-20160912. So far, my changes have been acked by Lars Persson, the original author of the binding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | wandboard: Make Ethernet functional againFabio Estevam2016-11-06-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate config for AR8031") ethernet does not work on mx6sabresd. This commit correctly assigns ar8031_config() as the configuration function for AR8031 in the same way as done in the Linux kernel. However, on wandboard design we need some additional configuration, such as enabling the 125 MHz AR8031 output that needs to be done in the board file. This also aligns with the same method that the kernel performs the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | mkimage: Allow including a ramdisk in FIT auto modeTomeu Vizoso2016-11-06-4/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds -i option that allows specifying a ramdisk file to be added to the FIT image when we are using the automatic FIT mode (no ITS file). This makes adding Depthcharge support to LAVA much more convenient, as no additional configuration files need to be kept around in the machine that dispatches jobs to the boards. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Simon Glass <sjg@chromium.org> Cc: Matt Hart <matthew.hart@linaro.org> Cc: Neil Williams <codehelp@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | travis-ci: Try harder to build all ARM targetsTom Rini2016-11-06-8/+39
| | | | | | | | | | | | | | | | | | | | | | The way that we have things broken down currently allows for some combinations of vendor or CPU to not be built. To fix this, create a new catch-all job that excludes everything we've built elsewhere. For the sake of simplicity we are allowing for the possibility of some overlap between the vendor-based jobs and the CPU-based jobs. While we're in here, make a failed build provide the summary of failure. Signed-off-by: Tom Rini <trini@konsulko.com>
* | buildman: Fix building based on 'options' fieldTom Rini2016-11-06-2/+2
|/ | | | | | | | | | The README for buildman says that we can use any field in boards.cfg to decide what to build. However, we were not saving the options field correctly. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* mx6sabresd: Make Ethernet functional againFabio Estevam2016-11-06-0/+33
| | | | | | | | | | | | | | | | | Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate config for AR8031") ethernet does not work on mx6sabresd. This commit correctly assigns ar8031_config() as the configuration function for AR8031 in the same way as done in the Linux kernel. However, on mx6sabresd design we need some additional configuration, such as enabling the 125 MHz AR8031 output that needs to be done in the board file. This also aligns with the same method that the kernel performs the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* engicam: icorem6: Fix config filesJagan Teki2016-11-05-3/+4
| | | | | | | | | Config file names on MAINTAINERS and README in board/engicam/icorem6 seems to be wrong, hence fixed the same. Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* armv8: define get_ticks() for the ARMv8 Generic TimerAndre Przywara2016-11-05-0/+11
| | | | | | | | | | | | | | | | | | | For 64-bit ARM systems we provide just a timer_read_counter() implementation and rely on the generic non-uclass get_ticks() function in lib/time.c to call the former. However this function is actually not 64-bit safe, as it assumes a "long" to be 32-bit. Beside the fact that the resulting uint64_t isn't bigger than "long" on 64-bit architectures and thus combining two counters makes no sense, we get all kind of weird results when we try to OR in the high value shifted by _32_ bits. So let's avoid that function at all and provide a straight forward get_ticks() implementation for ARMv8, which also is in line with ARMv7. This fixes occasional immediate time-out expiration issues I see on the Pine64 board. The root cause of this needs to be investigated, but this fix looks like the right thing anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* doc: update README.arm64Andre Przywara2016-11-05-10/+17
| | | | | | | This file apparently hasn't seen an update in a while, so just sync it with reality. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* tools: imximage: check return value when open the plugin filePeng Fan2016-11-05-1/+8
| | | | | | | | | | | | | | | | | | Check return value when open the plugin file. Coverity report: ** CID 153926: Error handling issues (NEGATIVE_RETURNS) /tools/imximage.c: 542 in copy_plugin_code() ifd = open(plugin_file, O_RDONLY|O_BINARY); >>> CID 153926: Error handling issues (NEGATIVE_RETURNS) >>> "ifd" is passed to a parameter that cannot be negative. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@konsulko.com> Reported-by: Coverity (CID: 153926) Reviewed-by: Tom Rini <trini@konsulko.com>
* image: Protect against overflow in unknown_msg()Simon Glass2016-11-05-2/+4
| | | | | | | | | | Coverity complains that this can overflow. If we later increase the size of one of the strings in the table, it could happen. Adjust the code to protect against this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 150964)
* colibri_pxa270: drop lzma support for space reasonMarcel Ziswiler2016-11-05-1/+0
| | | | | | | As the upcoming driver model integration takes up some more precious flash space first make sure to drop expensive LZMA support. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-11-03-2/+6
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| * dfu: align array in dfu_get_dev_type with enum dfu_device_typePatrick Delaunay2016-11-03-1/+1
| | | | | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
| * cmd: dfu: Add error handling for board_usb_initMichal Simek2016-11-03-1/+5
| | | | | | | | | | | | board_usb_init() can failed and error should be handled properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-11-02-183/+422
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| * rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORTKever Yang2016-10-30-3/+0
| | | | | | | | | | | | | | | | | | SPL_MMC_SUPPORT defined in rockchip top level Kconfig instead of inside rk3288 and default to disable if ROCKCHIP_SPL_BACK_TO_BROM defined. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: doc: add GPT partition layoutJacob Chen2016-10-30-2/+9
| | | | | | | | | | | | | | A simple introduction. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: use rockchip linux partitions layoutJacob Chen2016-10-30-46/+39
| | | | | | | | | | | | | | | | | | | | | | | | Unify the partitions of each chip then it will be more easy for us to write scripts, tools or guides for rockchip chips. Those extra partitions mostly are used to be compatible with our internal loaders (such as miniloader which was same as spl, or android loader then we can support dual boot) Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * dts: rk3288: remove node in dmc which not need anymoreKever Yang2016-10-30-18/+0
| | | | | | | | | | | | | | | | | | | | Since we implement the dram capacity auto detect, we don't need to set the channel number and sdram-channel in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * rk3288: sdram: auto-detect the capacityKever Yang2016-10-30-42/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for rk3288 dram capacity auto detect, support DDR3 and LPDDR3, DDR2 is not supported. The program will automatically detect: - channel number - rank number - column address number - row address number The dts file do not need to describe those info after apply this patch. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * rk3288: config change for enable dram capacity auto-detect.Kever Yang2016-10-30-0/+4
| | | | | | | | | | | | | | | | Enable ROCKCHIP_SPL_BACK_TO_BROM and disable CONFIG_SPL_MMC_SUPPORT to save memory in order to enable add source code for dram capacity auto-detect. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * evb-rk3399: config: set emmc as default boot devKever Yang2016-10-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | rk3399 has two mmc dev controller: mmc 0: SD card; mmc 1: EMMC U-Boot will scan the mmc boot device configured by CONFIG_SYS_MMC_ENV_DEV, since evb has emmc on board, let's set the EMMC as default. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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