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* arm: socfpga: spl: Toggle warm reset config I/O bitMarek Vasut2015-08-08-0/+5
| | | | | | | Synchronise the SPL behavior with the original Altera code and toggle the Warm Reset Config I/O bit accordingly. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-14/+43
| | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()Marek Vasut2015-08-08-5/+9
| | | | | | | | Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(), which allows both enabling and disabling the warm reset config I/O functionality. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-35/+54
| | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-13/+26
| | | | | | | | | It is sufficient to pass in the scan chain ID into the function to determine the remaining two parameters, so drop those params and determine them locally in the function. The big-ish switch in the function is temporary and will be replaced by a proper function call in subsequent patch. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-16/+9
| | | | | | | | This function is never used outside of scan_manager.c , so make it static. Zap the prototype in scan_manager.h and move the documentation above the function. Make the documentation kerneldoc compliant. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-129/+169
| | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: clock: Get rid of cm_config_t typedefMarek Vasut2015-08-08-5/+5
| | | | | | Get rid of this cryptic typedef and replace it with explicit struct cm_config. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Add SDMMC, QSPI and DMA definesMarek Vasut2015-08-08-0/+3
| | | | | | | Add SDMMC, QSPI and DMA reset defines. These are needed by SPL so that we can boot from SD card and QSPI. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Add function to reset add peripheralsMarek Vasut2015-08-08-0/+14
| | | | | | | Add socfpga_per_reset_all() function to reset all peripherals but the L4 watchdog. This is needed in the SPL. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Repair bridge reset handlingMarek Vasut2015-08-08-4/+4
| | | | | | | | | | | The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and in case it was (!), the code called hang(). This makes no sense at all. Repair it such that the code instead checks whether the FPGA is programmed, but without any polling involved, and only if it is programmed, it de-asserts the reset. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Replace ad-hoc reset functionsMarek Vasut2015-08-08-64/+13
| | | | | | | | Replace all those ad-hoc reset functions, which were all copies of the same invocation of clrbits_le32() anyway, with one single unified function, socfpga_per_reset(), with necessary parameters. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Implement unified function to toggle resetMarek Vasut2015-08-08-23/+37
| | | | | | | | Implement function socfpga_per_reset(), which allows asserting or de-asserting reset of each reset manager peripheral in a unified manner. Use this function throughout reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Start reworking the SoCFPGA reset managerMarek Vasut2015-08-08-19/+50
| | | | | | | | | | Implement macro SOCFPGA_RESET(name), which produces an abstract reset number. Implement macros which allow extracting the reset offset in permodrstN register and which permodrstN register the reset is located in from this abstract reset number. Use these macros throughout the reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Add missing reset manager regsMarek Vasut2015-08-08-0/+2
| | | | | | | Define two missing reset manager registers, which are in the SoCFPGA CV datasheet. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Fix debug message format in sequencerMarek Vasut2015-08-08-7/+7
| | | | | | | | | | The debug messages missed proper newlines and/or spaces in them. Fix the formatting. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@konsulko.com>
* ddr: altera: Fix typo in mp_threshold1 programmingMarek Vasut2015-08-08-1/+1
| | | | | | | | | | | It is the configuration data that should go into the register, not the register mask, just like the surrounding code does it. Fix this typo. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@konsulko.com>
* ddr: altera: Move struct sdram_prot_rule prototypeMarek Vasut2015-08-08-13/+13
| | | | | | | | | | | Move the structure prototype from sdram.h header file into sdram.c source file, since it is used only there and for local purpose only. There is no point in having it global. While at this move, fix the data types in the structure from uintNN_t to uNN and fix the coding style a bit. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Move sdram_config.h to board dirMarek Vasut2015-08-08-1/+6
| | | | | | | This file is absolutelly positively board specific, so move it into the correct place. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: enable the Altera SDRAM controller driverDinh Nguyen2015-08-08-0/+5
| | | | | | | Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* driver/ddr/altera: Add the sdram calibration portionDinh Nguyen2015-08-08-0/+4985
| | | | | | This patch adds the DDR calibration portion of the Altera SDRAM driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* driver/ddr/altera: Add DDR driver for Altera's SDRAM controllerDinh Nguyen2015-08-08-12/+1200
| | | | | | | | This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* net: designware: Rename the driver var name to eth_designwareMarek Vasut2015-08-08-1/+1
| | | | | | | | | The driver variable name is eth_sandbox, which is probably a copy-paste mistake. Fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: designware: Add SoCFPGA GMAC DT compatible stringMarek Vasut2015-08-08-0/+1
| | | | | | | | Add the OF compatible property to match the SoCFPGA GMAC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: Move generated files into qts subdirMarek Vasut2015-08-08-7/+14
| | | | | | | | | Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: dts: socfpga: Add mmc aliasMarek Vasut2015-08-08-0/+1
| | | | | | | Add alias for the SD/MMC controller, so it can be located by U-Boot OF support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: dts: socfpga: Fix SPI aliasesMarek Vasut2015-08-08-16/+5
| | | | | | | | | | | | | The SPI aliases are completely wrong. First, they point to non-existing /spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use ad-hoc string instead of a handle. Furthermore, they are copied multiple times in each board DTS. So fix it such that we move these into socfpga.dtsi and make them use the usual handles. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Fix FPGA bitstream programming routineMarek Vasut2015-08-08-0/+3
| | | | | | | | | In case the FPGA bitstream is aligned to 4 bytes, skip the part of the assembler which handles unaligned bitstream. Otherwise, that part will loop indefinitelly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-2291/+5743
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| * exynos: dts: Correct LDO and BUCK namingSimon Glass2015-08-06-63/+63
| | | | | | | | | | | | | | | | At present lower case is used for the regulator names in the device tree. The kernel uses upper case and U-Boot will require this also since it will move to a case-sensitive name check. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable debug UART for MinnowmaxSimon Glass2015-08-06-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the debug UART and emit a single 'a' early in the init sequence to show that it is working. Unfortunately the debug UART implementation needs a stack to work. I cannot seem to remove this limitation as the absolute 'jmp %eax' instruction goes off into the weeds. So this means that the character output cannot be any earlier than car_init_ret, where memory is available for a stack. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * dm: core: Fix a typo in the uclass_get_device_by_name() commentSimon Glass2015-08-06-1/+1
| | | | | | | | | | | | | | This function comment has a typo. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: core: Add a way to set a device nameSimon Glass2015-08-06-0/+25
| | | | | | | | | | | | | | | | | | | | Some devices are bound entirely by probing and do not have the benefit of a device tree to give them a name. This is very common with PCI and USB. In most cases this is fine, but we should add an official way to set a device name. This should be called in the device's bind() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * sandbox: Enable devres subsystemSimon Glass2015-08-06-0/+1
| | | | | | | | | | | | | | | | This should be used for sandbox. We can convert at least one driver to use it, but in the meantime, enable the feature so that the code is build-tested. Signed-off-by: Simon Glass <sjg@chromium.org>
| * devres: add debug command to dump device resourcesMasahiro Yamada2015-08-06-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new command can dump all device resources associated to each device. The fields in every line shows: - The address of the resource - The size of the resource - The name of the release function - The stage in which the resource has been acquired (BIND/PROBE) Currently, there is no driver using devres, but if such drivers are implemented, the output of this command should look like this: => dm devres - root_driver - soc - extbus - serial@54006800 bfb541e8 (8 byte) devm_kmalloc_release BIND bfb54440 (4 byte) devm_kmalloc_release PROBE bfb54460 (4 byte) devm_kmalloc_release PROBE - serial@54006900 bfb54270 (8 byte) devm_kmalloc_release BIND - gpio@55000000 - i2c@58780000 bfb5bce8 (12 byte) devm_kmalloc_release PROBE bfb5bd10 (4 byte) devm_kmalloc_release PROBE - eeprom bfb54418 (12 byte) devm_kmalloc_release BIND Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * devres: make Devres optional with CONFIG_DEVRESMasahiro Yamada2015-08-06-2/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, Devres requires additional 16 byte for each allocation, which is not so insignificant in some cases. Add CONFIG_DEVRES to make this framework optional. If the option is disabled, devres functions fall back to non-managed variants. For example, devres_alloc() to kzalloc(), devm_kmalloc() to kmalloc(), etc. Because devres_head is also surrounded by an ifdef conditional, there is no memory overhead when CONFIG_DEVRES is disabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * devres: add devm_kmalloc() and friends (managed memory allocators)Masahiro Yamada2015-08-06-0/+78
| | | | | | | | | | | | | | | | | | | | | | devm_kmalloc() is identical to kmalloc() except that the memory allocated with it is managed and will be automatically released when the device is removed/unbound. Likewise for the other variants. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * devres: introduce Devres (Managed Device Resource) frameworkMasahiro Yamada2015-08-06-1/+374
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In U-Boot's driver model, memory is basically allocated and freed in the core framework. So, low level drivers generally only have to specify the size of needed memory with .priv_auto_alloc_size, .platdata_auto_alloc_size, etc. Nevertheless, some drivers still need to allocate/free memory on their own in case they cannot statically know the necessary memory size. So, I believe it is reasonable enough to port Devres into U-boot. Devres, which originates in Linux, manages device resources for each device and automatically releases them on driver detach. With devres, device resources are guaranteed to be freed whether initialization fails half-way or the device gets detached. The basic idea is totally the same to that of Linux, but I tweaked it a bit so that it fits in U-Boot's driver model. In U-Boot, drivers are activated in two steps: binding and probing. Binding puts a driver and a device together. It is just data manipulation on the system memory, so nothing has happened on the hardware device at this moment. When the device is really used, it is probed. Probing initializes the real hardware device to make it really ready for use. So, the resources acquired during the probing process must be freed when the device is removed. Likewise, what has been allocated in binding should be released when the device is unbound. The struct devres has a member "probe" to remember when the resource was allocated. CONFIG_DEBUG_DEVRES is also supported for easier debugging. If enabled, debug messages are printed each time a resource is allocated/freed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: add DM_FLAG_BOUND flagMasahiro Yamada2015-08-06-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Currently, we only have DM_FLAG_ACTIVATED to indicate the device status, but we still cannot know in which stage is in progress, binding or probing. This commit introduces a new flag, DM_FLAG_BOUND, which is set when the device is really bound, and cleared when it is unbound. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: Support address translation for simple-busSimon Glass2015-08-06-6/+53
| | | | | | | | | | | | | | | | The 'ranges' property can be used to specify a translation from the system address to the bus address. Add support for this using the dev_get_addr() function, which devices should use to find their address. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: smsc95xx: Add driver-model supportSimon Glass2015-08-06-0/+142
| | | | | | | | | | | | | | Add support for driver model, so that CONFIG_DM_ETH can be defined and used with this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: smsc95xx: Prepare for conversion to driver modelSimon Glass2015-08-06-122/+150
| | | | | | | | | | | | | | | | At present struct eth_device is passed around all over the place. This does not exist with driver model. Add explicit arguments instead, so that with driver model we can pass the correct things. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: smsc95xx: Correct the error numbersSimon Glass2015-08-06-22/+26
| | | | | | | | | | | | | | Instead of returning -1 on error, we should use a proper error number. Fix the code to conform to this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: smsc95xx: Rename AX_RX_URB_SIZE to RX_URB_SIZESimon Glass2015-08-06-5/+5
| | | | | | | | | | | | | | The AX_ prefix comes from the Asix driver. Since this is not that, we should avoid this confusing prefix. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: smsc95xx: Sort the include filesSimon Glass2015-08-06-2/+3
| | | | | | | | | | | | Tidy up the include file order before adding more. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: usb: Add driver-model support to dwc2Simon Glass2015-08-06-0/+97
| | | | | | | | | | | | | | Add driver model support to this driver so it can be used with the new USB stack. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: usb: Prepare dwc2 driver for driver-model conversionSimon Glass2015-08-06-54/+104
| | | | | | | | | | | | | | Put all global data in a structure and move (what will be) common code into common functions. This will make the driver-model conversion much easier. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: usb: Add an errno.h header to usb_ether.cSimon Glass2015-08-06-0/+1
| | | | | | | | | | | | This is required on some platforms, so add it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Make regmap and syscon optionalSimon Glass2015-08-06-2/+22
| | | | | | | | | | | | | | | | Not all boards use garbage collection in their link step, so we should avoid adding options that rely on this for prevention of code bloat. Add separate Kconfig options for syscon and regmap uclasses. Signed-off-by: Simon Glass <sjg@chromium.org>
| * lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedefYork Sun2015-08-06-4/+2
| | | | | | | | | | | | | | | | | | fdt_addr_t is a physical address. It can be either 64-bit or 32-bit, depending on the architecture. It should be phys_addr_t instead of u64 or u32. Similarly, fdt_size_t is changed to phys_size_t. Signed-off-by: York Sun <yorksun@freescale.com> CC: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-09 15:24:49 +0000