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* dm: rtc: sandbox: Enable real-time clock supportSimon Glass2015-05-05-2/+2
| | | | | | Enable real-time-clock support in sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: dts: Add a real-time clock attached to I2CSimon Glass2015-05-05-1/+11
| | | | | | | Add an emulated RTC device for sandbox, so that the 'date' command can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: net: rtc: Support using driver model for rtc in sntpSimon Glass2015-05-05-0/+12
| | | | | | | When setting the date, support driver model RTC also. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: rtc: Convert 'date' command to support driver modelSimon Glass2015-05-05-14/+41
| | | | | | | Adjust this command so that it supports using driver model for I2C, i.e. CONFIG_DM_I2C. This will permit it to be used in sandbox also. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: rtc: sandbox: Add a driver for the sandbox I2C RTCSimon Glass2015-05-05-0/+109
| | | | | | | | Add a driver which communicates with the sandbox I2C emulation RTC device and permits it to be used in U-Boot. This driver is very simple - it just reads and writes selected I2C registers in the device. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: rtc: sandbox: Add an emulated I2C RTC deviceSimon Glass2015-05-05-0/+286
| | | | | | | | | | | | Add a sandbox I2C emulation device which emulates a real-time clock. The clock works off an offset from the current system time, and supports setting and getting the clock, as well as access to byte-width regisers in the RTC. It does not support changing the system time. This device can be used for testing the 'date' command on sandbox, as well as the RTC uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: rtc: Add a uclass for real-time clocksSimon Glass2015-05-05-0/+239
| | | | | | | | | Add a uclass for real-time clocks which support getting the current time, setting it and resetting the chip to a known-working state. Some RTCs have additional registers which can be used to store settings, so also provide an interface to these. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: Add os_localtime() to obtain the system timeSimon Glass2015-05-05-0/+29
| | | | | | Add a function to read the system time into U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: rtc: Split structure definition into its own fileSimon Glass2015-05-05-25/+37
| | | | | | | Move the definition of struct rtc_time into a separate file so that sandbox can include it without requiring common.h and the like. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Remove unnecessary types in bcd.hSimon Glass2015-05-05-5/+3
| | | | | | | | We don't need to use u8, and if we avoid it, it isn't so much of a problem that rtc.h includes this header. With this change we can include rtc.h from sandbox files. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: rtc: Rename mktime() and reduce the number of parametersSimon Glass2015-05-05-41/+54
| | | | | | | | | Most callers unpack the structure and pass each member. It seems better to pass the whole structure instead, as with the C library. Also add an rtc_ prefix. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* dm: rtc: Rename to_tm() to rtc_to_tm() and add error codeSimon Glass2015-05-05-19/+36
| | | | | | | | | | Rename this function so that it is clear that it is provided by the RTC. Also return an error when it cannot function as expected. This is unlikely to occur since it works for dates since 1752 and many RTCs do not support such old dates. Still it is better to be accurate. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* dm: rtc: Rename gregorian day functionSimon Glass2015-05-05-5/+20
| | | | | | | | Change this function name to something more descriptive. Also return a failure code if it cannot calculate a correct value. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* fdt: Correct warning in fdt_setup_simplefb_node()Simon Glass2015-05-05-1/+1
| | | | | | Adjust the printf() string to avoid a warning on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Add an explicit test mode to the sandbox I2C driverSimon Glass2015-05-05-11/+42
| | | | | | | | | At present this driver has a few test features. They are needed for running the driver model unit tests but are confusing and unnecessary if using sandbox at the command line. Add a flag to enable the test mode, and don't enable it by default. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Add functions to read and write a registerSimon Glass2015-05-05-0/+40
| | | | | | | | Add driver model versions of the legacy functions to read and write a single byte register. These are a useful shortcut in many cases. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* dm: i2c: sandbox: Add debugging to the speed limitSimon Glass2015-05-05-1/+3
| | | | | | | Print a debug() message with the I2C speed is exceeded. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* dm: spi: Correct the comment on spi_get_ops()Simon Glass2015-05-05-1/+1
| | | | | | | This comment should refer to SPI, not serial. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* cros_ec: Handle the single duplex requirement in cros_ecSimon Glass2015-05-05-3/+20
| | | | | | | With several chips using the SPI protocol it seems better to put the single duplex functionality in the EC rather than the SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Show the protocol version in the debug messageSimon Glass2015-05-05-1/+2
| | | | | | | When starting up, show the protocol version that has been negotiated with the EC. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Avoid setting the speed with every transferSimon Glass2015-05-05-3/+9
| | | | | | | | Only set the speed if it has changed from last time. Since the speed will be 0 when the device is probed it will always be changed on the first transfer after the device is probed. Signed-off-by: Simon Glass <sjg@chromium.org>
* test: dm: eth: Skip timeouts on ping testsJoe Hershberger2015-05-05-0/+2
| | | | | | | | Indicate to the emulated sandbox Ethernet driver when we expect a timeout and tell it to leap forward. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: eth: Add a function to skip ping timeoutsJoe Hershberger2015-05-05-0/+19
| | | | | | | | | When called, the next call to receive will trigger a 10-second leap forward in time to avoid waiting for time to pass when tests are evaluating timeout behavior. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: Add test function to advance timeJoe Hershberger2015-05-05-6/+18
| | | | | | | | | | Add a function that maintains an offset to include in the system timer values returned from the lib/time.c APIs. This will allow timeouts to be skipped instantly in tests Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* Prepare v2015.07-rc1Tom Rini2015-05-05-2/+2
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* fw_env.h: include autoconf.hMax Krummenacher2015-05-05-0/+1
| | | | | | | | | | | | | | Without this, when CONFIG_ENV_VARS_UBOOT_CONFIG is active we get a compile time error when doing 'make env'. In file included from tools/env/fw_env.c:117:0: include/env_default.h:110:11: error: expected ‘}’ before ‘CONFIG_SYS_ARCH’ When building U-Boot this is included indirectly by the compiler switch -include /home/trdx/git.toradex.com/u-boot-2014.10-toradex/include/linux/kconfig.h Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2015-05-05-510/+3241
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| * powerpc/mpc85xx: Add board support for ucp1020Oleksandr G Zhadan2015-05-04-0/+2298
| | | | | | | | | | | | | | | | | | | | New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> [York Sun: remove patman tags from commit message] Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Fix compiling error for common/cmd_gpio.cOleksandr G Zhadan2015-05-04-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To replicate: 1. add to include/configs/p1_p2_rdb_pc.h "#define CONFIG_CMD_GPIO" 2. run `make P1020RDB-PC_defconfig` 3. run CROSS_COMPILE=powerpc-linux- make and you will get: common/built-in.o: In function `do_gpio': u-boot/common/cmd_gpio.c:186: undefined reference to `gpio_request' u-boot/common/cmd_gpio.c:194: undefined reference to `gpio_direction_input' u-boot/common/cmd_gpio.c:195: undefined reference to `gpio_get_value' u-boot/common/cmd_gpio.c:200: undefined reference to `gpio_get_value' u-boot/common/cmd_gpio.c:203: undefined reference to `gpio_direction_output' u-boot/common/cmd_gpio.c:209: undefined reference to `gpio_free Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t4240qds: Update RCW, defconfig and maintainerShaohui Xie2015-05-04-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. board/freescale/t4qds/t4_rcw.cfg 1.8GHz support is requested as default frequency, so update the rcw. 2. remove un-used configs configs/T4160QDS_SPIFLASH_defconfig configs/T4240QDS_SPIFLASH_defconfig SPI boot is not available on T4QDS, so the configs should be removed. 3. board/freescale/t4qds/MAINTAINERS Updated MAINTAINERS accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> [York Sun: revise subject] Reviewed-by: York Sun <yorksun@freescale.com>
| * t2080rdb/rcw: update ddr frequency from 1600MT/s to 1867MT/sShengzhou Liu2015-05-04-1/+4
| | | | | | | | | | | | | | | | | | T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s. So update RCW to support new DDR frequency 1867MT/s by default. Reserve the old 1600MT/s in comment for users in needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t2080qds: enable eSDHC peripheral clock supportYangbo Lu2015-05-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | Enable eSDHC peripheral clock support. u-boot and linux will use SD clock generated by peripheral clock instead of platform clock. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mmc: fsl_esdhc: Add peripheral clock supportYangbo Lu2015-05-04-3/+102
| | | | | | | | | | | | | | | | | | | | | | | | The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t2080qds: enable eSDHC adapter card type identificationYangbo Lu2015-05-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | Enable eSDHC adapter card type identification and this will do some corresponding operations and set 'adapter-type' property for device tree according SDHC Card ID. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mmc: fsl_esdhc: Add adapter card type identification supportYangbo Lu2015-05-04-6/+90
| | | | | | | | | | | | | | | | | | | | | | | | Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
| * board/t2080rdb: reset cs4315 phyShengzhou Liu2015-05-04-0/+10
| | | | | | | | | | | | | | | | CS4315 PHY doesn't support phy-reset by software, it needs to reset it by hardware via CPLD control. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/deepsleep: avoid the DDR restore from being optimized outTang Yuantian2015-05-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | Function dp_ddr_restore is to restore the first 128-byte space of DDR. However those codes may be optimized out by compiler since the destination address is at 0x0. In order to avoid compiler optimization, we restore the space from high address, which is not at 0x0, to low address. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Don't deref NULL if qman portal lacks cell-indexScott Wood2015-05-04-2/+7
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/t102x: use fdt_setprop_string instead of fdt_setpropShengzhou Liu2015-05-04-6/+7
| | | | | | | | | | | | | | Use fdt_setprop_string instead of fdt_setprop to fix string length. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc: add 2 common dcache assembly functionsValentin Longchamp2015-05-04-164/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t1023rdb: Add T1023 RDB board supportShengzhou Liu2015-05-04-44/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix defconfig files] Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/pci: Set CFG_READY for PCIe v3.0 and laterMinghuan Lian2015-05-04-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issueZhao Qiang2015-05-04-0/+16
| | | | | | | | | | | | | | | | | | T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t4rdb: Add SD boot support for T4240RDB boardChunhe Lan2015-05-04-16/+186
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: Fix T4240RDB_SDCARD_defcofig] Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: usb: fsl: Workaround for Erratum A004477Nikhil Badola2015-05-04-0/+49
| | | | | | | | | | | | | | | | | | | | Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx/T4240EMU: Remove T4240EMU boardYork Sun2015-05-04-234/+0
| | | | | | | | | | | | | | T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Use GOT when loading IVORs post-relocationScott Wood2015-05-04-15/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") simplified IVOR initialization a bit too much, failing to use the post-relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Alexander Graf <agraf@suse.de> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-05-05-60/+379
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| * | arm: mvebu: Remove "u-boot.kwb" CONFIG_BUILD_TARGET for non-SPL targetsStefan Roese2015-05-05-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By removing this default build target, the "u-boot.kwb" target is not automatically generated. This fixes a temporary build error when using out-of-tree builds, as buildman does per default (reported by Simon). When the full SPL support is added for these targets with the DDR training code, the "u-boot-spl.kwb" image will be generated automatically. Users providing a special bin_hdr binary (binary.0) file can always add this binary file and generate the full firmware image by issuing the "make u-boot.kwb" command directly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-mv784mp-gp: Fix ECC I2C addressStefan Roese2015-05-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The macro to select the I2C address for ECC bus-width detection was defined incorrectly for the Marvell DB-MV784MP-GP board. This patch changes the macro to the correct value to fix this issue. Signed-off-by: Stefan Roese <sr@denx.de>
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