| Commit message (Collapse) | Author | Age | Lines |
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The single message is misleading, since there is no equivalent success
note when reading the other copy succeeds. Instead, warn if one of the
redundant copies could not be loaded and emphasise on the error when
reading both fails.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
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If the NAND is locked tight, commands such as lock and unlock will not
work, but the NAND chip may not report an error. Check the lock tight
status before attempting such operations so that an error status can be
reported if we know the operation will not succeed.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
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"nand read.part addr off size" would be treated as "nand read.raw addr off 1"
It now fails as intended stating "Unknown nand command suffix '.part'"
Signed-off-by: Harvey Chapman <hchapman@3gfp.com>
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This patch adds support to list images in NAND flash through imls
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
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Add support for per architecture CROSS_COMPILE toolchain definitions
via CROSS_COMPILE_ARCH where "ARCH" is any of the supported u-boot
architectures. This allows building every supported u-boot board in a
single pass of MAKEALL.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
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Currently, in gpt command, partion size is converted from string
to unsigned long type using 'ustrtol' function. That type limits
the partition size to 4GB.
This patch changes the conversion function to 'ustrtoll' to return
unsigned long long type.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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The issue got introduced in a cleanup by Manjunath Hadli in commit
826e99136e2bce61f3f6572e32d7aa724c116e6d. The eth_getenv_enetaddr_by_index
method will validate the MAC addr and if none is set in the environment
0 will be returned. Set the MAC from the eeprom if no valid address
is found in environment.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
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u-boot is not consistent if state should be 0|1 or of the enum, the
GPIO driver expects this to be one of the enum values. Update the
caller.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
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The differences include the number of GPIOs and that one is
not required to set the pinmux on request.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
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Fix broken bootvx command.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
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Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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Fix a comment in the fw_env.config file, no functional change.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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Add 'ustrtoull' function to convert size from string (ex: 1GiB)
to unsigned long long type
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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On architectures where manual relocation
is needed, the 'malloc_bin_reloc' function
must be called after 'mem_malloc_init'.
Make the 'malloc_bin_reloc' function static
and call it directly from 'mem_malloc_init'
instead of calling that from board_init_{r,f}
functions of the affected architectures.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andreas Bießmann <andreas.devel@gmail.com>
Cc: Jason Jin <Jason.jin@freescale.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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This saved 640 bytes on MPC8536DS (a board with two of the six
ports defined).
Signed-off-by: Scott Wood <scottwood@freescale.com>
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There is no need for a environment variable to configure the dtt bus.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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Remove it from the processor specific headers. This is
already defined in the common header km83xx.h.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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This board is similar to TUXX1 but it has a different sized second
FPGA. Therefore the configuration for the third chipselect is different.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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This is a preparation for the upcoming kmopti2 board. This board has
also a second fpga on board which is different to the tuxx1 target. But we
want to use the same header file. So remove the config option
KM_DISABLE_APP2 and simply use the board names to distinguish the features.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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If CONFIG_NAND_ECC_BCH is chosen from in the board configuration we add
an ecc mode to the kernel commandline.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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Switch from 1-bit ecc to 4-bit ecc.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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If CONFIG_NAND_ECC_BCH is set we use 4-bit error corretion code
instead of the 1-bit error correction code on the NAND device
within this driver.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
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Replace uImage with ${uimage}.
If uimage is not set, default it to uImage.
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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Replace the hardcoded string with a variable. If CONFIG_NAND_ECC_BCH is
set we use a specific name for the uImage (ecc_bch_uImage).
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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On this board we are using hard floating point, so select the correct
toolchain.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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kmvect1 has a UEC2 connection to the piggy board and a UEC0 connection
to the switch MV88E6122. This switch has a connection to a frontport
ethernet interface. The ethernet port used for network booting is
automatically selected by u-boot. If a Piggy is plugged, the Piggy
port is selected (UEC2, eth1). If the Piggy isn't present, the
Frontport is selected (UEC0, eth0).
The switch reset is connected to a GPIO on the PRIO3 board FPGA (GPIO28)
and released at startup.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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For the the kmvect1 board we will also need a functionality to add an
offset to the IVMs MAC address, because these board will have two valid
ethernet ports for debugging purpose. So move the code to an own
function.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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For kmvect1 we need a special solution and for km_arm boards we already
have. So move the common code to the architectur specific file.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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This define isn't set within our setup files. So we can safely remove
the affected code.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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EEprom_ivm_addr isn't set in our environment, so remove the usage of
this.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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All boards from this serie use i2c. There is no need to #ifdef the
header.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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This is available on other architectures, and nds32 will start to break
without it as code starts to use error numbers more.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Adding CPU detection support for the DRA752 ES1.0 soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
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Adding the build support for dra7xx_evm.
Reusing omap5_evm.h config by moving it to omap5_common.h
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
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Adding new board files for DRA7XX socs.
The pad registers layout is changed completely from OMAP5
So introducing the new structure here and also adding the
minimal data.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishant Kamat <nskamat@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Adapt omap_mmc_init call for last 2 params]
Signed-off-by: Tom Rini <trini@ti.com>
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DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
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Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
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A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
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PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
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After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
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Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
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Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.
While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x
Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
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PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
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Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
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