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* MLK-10827 imx: mx6 update thermal driver according new equationPeng Fan2015-05-06-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC guys: " After a thorough accuracy study of the Temp sense circuit, we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. Old Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) Where Troom,cal = 25C and Slope = 0.4297157 – (0.0015974 * Count room fuse) New Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset Where Troom,cal = 25C and Slope = 0.4445388 – (0.0016549 * Count room fuse) Offset = 3.580661 " According the new equation, update the thermal driver. c1 and c2 changed to u64 type and update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10817 imx:mx6ul_ddr3_arm2 add mx6ul ddr3 arm2 board supportPeng Fan2015-05-05-0/+1762
| | | | | | | | | | | | | Add board code for mx6ul ddr3 arm2 board. QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR Add sd1, qspi and spinor boot support DDR script is 1.02 version. Signed-off-by: Fugang Duan <b38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10821 imx: mx6ulevk: Add board support for mx6ulevkYe.Li2015-05-05-0/+1570
| | | | | | | | | | | Add BSP codes to support modules on the board: I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial DDR version: 1.0 Build target: mx6ulevk_config mx6ulevk_qspi1_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-6 net: fec: add platform check to avoid to access the reserved ↵Peng Fan2015-05-05-1/+4
| | | | | | | | | register Add platform check to avoid to access the reserved register Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-5 imx: qspi i.MX6UL needs at least 16 bytes when writePeng Fan2015-05-05-2/+2
| | | | | | i.MX6UL qspi controller also needs at least 16 bytes when writing. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-4 mxc:gpio Add MX6UL supportPeng Fan2015-05-05-0/+4
| | | | | | comment out GPIO6/7 for MX6UL Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-3 imx:mx6ul PAD_CTL_SPEED_LOW for mx6ulPeng Fan2015-05-05-1/+1
| | | | | | PAD_CTL_SPEED_LOW for mx6ul same with mx6sx. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-2 imx:mx6ul add clock supportPeng Fan2015-05-05-61/+421
| | | | | | | | | | | | add i.MX6UL clock related settings/macros/apis When using TFT43AB, its pixel size is 480x272 which needs a slow pix clock. Without apply the test_div in PLL video, we can't get the pix clock in the rate. So change the LCDIF clock calculation to use the test_div. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-1 imx:mx6 add i2c4 supportPeng Fan2015-05-05-8/+28
| | | | | | I2C4 support for i.MX Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10808-5 imx: mx6ul: Update soc relevant settingsYe.Li2015-05-05-9/+25
| | | | | | | Remove PCIe, xPU power, PL310 L2 Cache for MX6UL. Update FEC MAC address, WDOG settings, USDHC clock rate. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-4 imx: Move system counter driver to imx-commonYe.Li2015-05-04-11/+28
| | | | | | | | | | | | | Since the system counter driver will also be used by mx6ul, move this timer driver to imx-common and rename it as syscounter.c For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default). GPT timer: CONFIG_GPT_TIMER System counter timer: CONFIG_SYSCOUNTER_TIMER Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-3 imx: mx6ul: Update imx registers head fileYe.Li2015-05-04-33/+114
| | | | | | Update imx registers base address for i.MX6UL Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-2 imx: mx6ul: Add pins IOMUX head fileYe.Li2015-05-04-0/+1068
| | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-1 imx: mx6ul: Add i.MX6UL CPU typeYe.Li2015-05-04-2/+5
| | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime. The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value has been occupied by i.MX6D as a dummy CPU type. So we also need change i.MX6D to a invalid value 0x67. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10774-53 imx: update setting pmic volatagePeng Fan2015-04-29-8/+179
| | | | | | | | We should not rely on pfuze_common_init to set the voltage, may be we should remove the voltage settings in pfuze_common_init. This patch is to setting the voltages in power_init_board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-52 nand: mxs correct MXS_DMA_ALIGNMENTPeng Fan2015-04-29-1/+1
| | | | | | | | | | | | We should align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN, otherwise we may encounter errors, " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10733 imx: imx6qpsabreauto: Update IPU QoS settingsLiu Ying2015-04-29-3/+3
| | | | | | | | | | | | | | Update IPU QoS settings from 0x007f007f to 0x77177717 according to the SoC team's recommendation. This change should be able to balance AXI ID0/2/3 priority and set AXI ID1 priority relatively lower, which matches the way we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs, IDMAC27 and IDMAC28 respectively in kernel. The specific priority values for each AXI ID are supposed to be picked for the sake of an overall good system performance. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 7c4bee613dc47c9e2fb147a159236bca04b8618b)
* MA-6580 recovery.img cannot be authenticated by HABguoyin.chen2015-04-29-9/+13
| | | | | | | | | | Remove the authentication size to be a fixed size, due to recovery.img may be much bigger than the boot.img Add signature size to boot or recovery image size, which is added by boot_signer in android build process Signed-off-by: guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit d59b24fefcd56d085c4010643ca9f6522a3cc58a)
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2015-04-29-4/+4
| | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
* MLK-10702 imx: mx7d: clock: correct fec MDC root clockFugang Duan2015-04-29-1/+1
| | | | | | | | In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not ipg clock, correct it. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
* MLK-10701 net: fec_mxc: setup right value for mdio hold timeFugang Duan2015-04-29-1/+3
| | | | | | | | | | | | | | The minimal hold time according to IEE802.3 (clause 22) is 10 ns. HOLDTIME + 1 is the number of clk cycles the fec is holding the output. Set the right hold time value when the MDC root clock is greater than 100Mhz. The issue was reported on i.MX28 and is fixed by Uwe Kleine-König in kernel: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/ drivers/net/ethernet/freescale/fec_main.c?id=63c607321492c5efc7a31bc4ea734b877f8e7f87 Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 0373a160e7f698064a6625e85f9120b6c81c1b61)
* MLK-10774-51 imx: Add epdc default configuration filePeng Fan2015-04-29-0/+28
| | | | | | Add epdc default configuration file. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-50 imx:mx7dsabresd move VIDEO config before EPDCPeng Fan2015-04-29-16/+16
| | | | | | Move VIDEO config to the front of EPDC Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00315894-34 imx6:dlsabresd/slevk Fix build break when enables EPDCYe.Li2015-04-29-11/+14
| | | | | | | | | | | | | -Use the new pins' name for imx6dl. -Change the read/write to registers by using register structure. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 66e7a93ff1e47d0e47627a984bcf2337db4f3bbf) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: board/freescale/mx6sabresd/mx6sabresd.c Remove imx6dl part, since already fixed.
* MLK-10774-49 imx: pcie update to align with imx_v2014.04Peng Fan2015-04-29-4/+87
| | | | | | | Update pcie code to align with imx_v2014.04. Mainly add DEBUG related stuff. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-48 imx: mx7 update hab_caam_clock_enablePeng Fan2015-04-29-11/+8
| | | | | | | Merge hab_caam_clock_enable and hab_caam_clock_disable into one function Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLRPeng Fan2015-04-29-0/+3
| | | | | | | | | | | This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
* MLK-10774-47 imx: mx7dsabresd enable thermalPeng Fan2015-04-29-0/+2
| | | | | | Enable thermal for mx7dsabresd board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2015-04-29-0/+38
| | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
* MLK-10674-1 imx: mx6qpsabreauto Update to 1.05 DDR ScriptPeng Fan2015-04-29-1/+9
| | | | | | | | | | | | | | | | | | | | Update to 1.05 ddr script, url: http://compass.freescale.net/livelink/livelink?func=ll& objId=233944823&objAction=browse&viewType=1 File name: arik_r2_sabre_ddr3_528_1.05c.inc Update: Read latency Aging control for IPU1/PRE0/PRE3 Aging control for IPU2/PRE1/PRE2 Test results: 3 boards passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
* MLK-10504 imx: mx6dqarm2: Fix CCM setting for lpddr2 400Mhz supportYe.Li2015-04-29-0/+6
| | | | | | | | | | | | | | | | | | Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 7490062ff86e1132b95bf153091f28f7940c0cf9)
* MLK-10658 imx: mx7d 12x12 arm2: Update plugin codes to use latest DDR scriptYe.Li2015-04-29-23/+27
| | | | | | | | | | The LPDDR3 intialization in plugin codes were missed to update in previous DDR script upgrading. So update the plugin codes to LPDDR3 script: 7D_lpddr3_0_2.ds5 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 1874cec3a70adde2ea911a9c155fb41c43ccab61)
* MLK-10655 Video: Fix second line string display issueYe.Li2015-04-29-4/+5
| | | | | | | | | | The string display on second line repeats the last word of first line and does not show full. This is the bug introduced by the fixing to MLK-10542. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ac430cee8c42f0acad9e126631d772b99f1166ea) (cherry picked from commit ff62c5b275a9b5e47d570d3eb10622799bf12070)
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-29-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
* MLK-10774-46 imx:mx6sx use correct GPR addressPeng Fan2015-04-29-1/+1
| | | | | | Use correct GPR address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-45 imx:mx6sx add SION for i2c pin muxPeng Fan2015-04-29-20/+20
| | | | | | | | Add SION for i2c pin mux, otherwise will cause error. Found this problem on mx6sxsabreauto board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-44 imx:mx6 fix is_soc_revPeng Fan2015-04-29-1/+1
| | | | | | | is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-43 imx:mx7d fix DEFAULT_FDT_FILEPeng Fan2015-04-29-5/+5
| | | | | | should add '\' to string, otherwise this macro will be ignored. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10542 video: Support multiple lines version string displayYe.Li2015-04-29-7/+23
| | | | | | | | | | | | The caculation of left space for version string is not correct, should use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space than actual have and cause string to overlay logo picture. Also current version string display only supports two lines words at max. This also causes overlay when the LCD pixel colume size is not enough. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ed53487d36a886fb4557088804a4b5232b168889)
* MLK-10617 imx: mx7d 12x12 arm2: Update LPDDR3 script to 7D_lpddr3_0_2.ds5Ye.Li2015-04-29-1/+1
| | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] This script enable MDLL, but make it much more margin for the unlock state . [DDR stress test result] 2 boards run the memtester for 3 days, and passed. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6fa6765b0dcdad8d414931e49edf6ba65a73d23a)
* MLK-10597: arm: imx7d: extend iomuxc-lpsr IO pads config optionsAdrian Alonso2015-04-29-4/+39
| | | | | | | | | * Extend IOMUXC-LPSR IO pads configuration options * Add alternative configuration modes for IO pads from IOMUXC-LPSR Signed-off-by: Adrian Alonso <aalonso@freescale.com> (cherry picked from commit ca20aa7ca0c21b9766e0c34cfec275aaab0f11e7)
* MLK-10569 imx7d: call set_epdc_qos unconditionallyRobby Cai2015-04-29-4/+1
| | | | | | | | | This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. This patch remove the #ifdef to make sure set_epdc_qos be called always. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit d2fb113740b2c67958862503dda2a40191ab0899) (cherry picked from commit 581aa86581bb1178c5df4ad5298e5b85c53f1186)
* MLK-10590: arm :imx7d: correct iomuxc-lpsr daisy chainAdrian Alonso2015-04-29-3/+3
| | | | | | | | | | * Correct daisy chain settings for LPSR iomux controller * Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified to be part of lpsr-iomuxc domain Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit e4fd6550b3e5458aaf5049a7e6a12d6e4443c53a)
* MLK-10522-3: imx: mx7d_12x12_ddr3_arm2: add target board supportAdrian Alonso2015-04-29-0/+750
| | | | | | | | | | | | | | * Add mx7d_12x12_ddr3_arm2 target board support * Initial support for mx7d_12x12_ddr3_arm2 target board add support for base hardware eMMC, SD and ECSPI boot. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 51d69f7996cc6e6da8bb3f0af751549cb2435e44) Conflicts: boards.cfg
* MLK-10522-2: arm: imx7d: add iomuxc-lpsr i2c pad settingsAdrian Alonso2015-04-29-1/+4
| | | | | | | | | | | * Add IMX7D iomuxc-lpsr I2C1 and I2C2 pad configuration settings * Input select offset input_sel_ofs = 0x05xx + IOMUX_LPSR_SEL_INPUT_OFS allows to access register in iomuxc controller for imx_iomux_v3_setup_pad I2C daisy chaing configuration. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit bca65c5ee1099f99b880be325c9fa0a568ab88de)
* MLK-10522-1: mx7d_arm: allow override mtest settingsAdrian Alonso2015-04-29-0/+2
| | | | | | | | | * Allow to override mtest settings for target board variants that differs on physical sdram memory size Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6173a3954b83ce22e24c62bc8ee922007b0929a6)
* MLK-10566: arm :imx7d: fix iomuxc-lpsr daisy chain settingsAdrian Alonso2015-04-29-0/+4
| | | | | | | | | | | | | | | * For IOMUXC LPSR pads when daisy chain register needs to be set the result offsets for sel_input register is incorrect as base address is 0x302C0000 and the passed offset does not resolve to the intended input sel pad register; input sel base offset should start in 0x30330000. * Add an addiotional fixed offset of 0x70000 to address the input sel offset: INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5d4612613eb2e85f1929d8cf5cb6aac6ba9e5fd7)
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2015-04-29-0/+3
| | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640)
* MLK-10568 imx: mx7d arm2: Update LPDDR3 script to 7D_lpddr3_0_1.ds5Ye.Li2015-04-29-19/+16
| | | | | | | | | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelinkfunc=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] 1. Change the DDR freq to 528Mhz. 2. Disable ddr phy dll, just force a dll output. IC suspects the dll in ddr phy may unlock sometimes. The side-effect is we will lost the ability to compensate the voltage/temperature change, so it may easy to fail at H/L temperature. [DDR stress test result] 3 boards involved the two days stress test by using memtester tool. One board met a kernel oops after one day test. Other two pass the two days test. Compared to previous DDR script, the result is much positive. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 843c3c54af12cbf20e7bc912178e5a3628b78198)
* MLK-10567: Extend u-boot imximage to support check bits set/clrNitin Garg2015-04-29-15/+29
| | | | | | | | | | | Add support for HAB "Check data" all bits set and clear check functionality. Rename CHECK_DATA to CHECK_BITS_SET. Flag=0 -> (*address & mask) == 0 | All bits clear Flag=2 -> (*address & mask) == mask | All bits set Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 0836912ef7a53d1f3d65f95556a34d03b8d65399)
generated by cgit v1.1 at 2024-11-18 12:04:08 +0000