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| * drivers/fsl-mc: Autoload AOIP image from NOR flashJ. German Rivera2015-07-20-0/+29
| | | | | | | | | | | | | | | | | | Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_confPrabhakar Kushwaha2015-07-20-0/+1
| | | | | | | | | | | | | | | | Flush buffer before releasing to BMan after TX_conf to ensure, the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Make MC boot error messages more readableJ. German Rivera2015-07-20-18/+13
| | | | | | | | | | | | | | | | | | Make it easier for the user to notice when the MC firmware had problems booting. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: enable debug serverStuart Yoder2015-07-20-0/+1
| | | | | | | | | | | | Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvrPrabhakar Kushwaha2015-07-20-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/errata: Update required bits for A57 cores erratasBhupesh Sharma2015-07-20-4/+4
| | | | | | | | | | | | | | | | | | | | This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/fsl_debug_server: Fix the DDR hide logic for LS2085aBhupesh Sharma2015-07-20-8/+5
| | | | | | | | | | | | | | | | | | | | This patch fixes the DDR hide logic for LS2085a, correcting the way the Debug Server FW and MC FW images are placed on the top of system DDR and how the rest of the system DDR space is made visibile to Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha2015-07-20-0/+25
| | | | | | | | | | | | | | | | | | | | Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Expose all DDR region(s) to LinuxBhupesh Sharma2015-07-20-18/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows u-boot to expose the complete DDR region(s) to Linux (after subtracting the memory hidden via MEM_TOP_HIDE mechanism). This allows the u-boot to support the 48-bit VA support provided by ARM64 Linux in flavors 3.18 and above, by passing the appropriate 'memory' DTS nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Fix SPD address error on early boardsYork Sun2015-07-20-2/+21
| | | | | | | | | | | | | | | | | | Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * driver/ddr/fsl: Add a hook to update SPD addressYork Sun2015-07-20-0/+11
| | | | | | | | | | | | | | | | In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * armv8/ls2085a: Avoid hard-coding for board name printPrabhakar Kushwaha2015-07-20-7/+9
| | | | | | | | | | | | | | | | | | | | | | LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A personlities. Instead of hard-coding, board name should change as per selected personality. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha2015-07-20-0/+57
| | | | | | | | | | | | | | | | | | | | | | This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Fix DDR speed messageYork Sun2015-07-20-2/+2
| | | | | | | | | | | | | | DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * armv8/ls2085RDB: Update board version print logicPrabhakar Kushwaha2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | As per updated board document, no need to substract 1 from arch[BRD] bit field. Default value + 'A' represents the board revision. So update board version print logic to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/fsl/common: Fix eeprom system version endiannessJaiprakash Singh2015-07-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | SYSTEM ID EPPROM always store SYSTEM version info in big endian format. SoC with ARM or PowerPC core should read/write version info from eeprom in BIG endian format. So use cpu-specific APIs to read SYSTEM version. Signed-off-by: Jaiprakash Singh <b44839 at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Increase the supported kernel sizeBhupesh Sharma2015-07-20-5/+8
| | | | | | | | | | | | | | | | | | | | | | Increases the kernel size supported for LS2085A platforms:- - Update environment variables - Add ramdisk_size in bootargs env variable - Define CONFIG_SYS_BOOTM_LEN to 64MB Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085rdb: Update PCA9547PW slave addressPrabhakar Kushwaha2015-07-20-2/+2
| | | | | | | | | | | | | | | | Primary Mux on I2C1 controller has slave address as 0x75. So update its address. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085qds: Update SFP TX bit as "0" to enable XFIPrabhakar Kushwaha2015-07-20-1/+1
| | | | | | | | | | | | | | | | FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports. Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha2015-07-20-0/+4
| | | | | | | | | | | | | | | | | | call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Update LS2085a PCIe compatiblePrabhakar Kushwaha2015-07-20-1/+2
| | | | | | | | | | | | | | | | | | Compatible field "fsl,20851a-pcie" is not correct. So update it to "fsl,ls2085a-pcie" Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: Add support of SerDes protocol 0x49Prabhakar Kushwaha2015-07-20-0/+2
| | | | | | | | | | | | | | | | | | | | SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2. Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of ls2085aqds platform. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Enable "date" command for QDS and RDBPriyanka Jain2015-07-20-0/+2
| | | | | | | | | | | | | | | | Enable "date" command for QDS and RDB boards Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: add hwconfig setting for eSDHCYangbo Lu2015-07-20-0/+38
| | | | | | | | | | | | | | | | | | Add hwconfig setting for eSDHC since it shares some pins with other IP block. Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Add eth & phy firmware loading supportPrabhakar Kushwaha2015-07-20-14/+157
| | | | | | | | | | | | | | | | | | | | Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | libfdt: fix error code of fdt_count_strings()Masahiro Yamada2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, this function returns a positive value on error, so we never know whether this function has succeeded or failed. For example, if the given property is not found, fdt_getprop() returns -FDT_ERR_NOTFOUND, and then this function inverts it, i.e., returns FDT_ERR_NOTFOUND (=1). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: bc4147ab2d69 ("fdt: Add a function to count strings") Acked-by: Simon Glass <sjg@chromium.org>
* | libfdt: fix error code of fdt_get_string_index()Masahiro Yamada2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | As mentioned in the comment block in include/libfdt.h, fdt_get_string_index() is supposed to return a negative value on error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings") Acked-by: Simon Glass <sjg@chromium.org>
* | libfdt: fix description of fdt_get_string()Masahiro Yamada2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | Looks like this comment was copied from that of fdt_get_string_index(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings") Acked-by: Simon Glass <sjg@chromium.org>
* | cmd_fdt: save fdtaddr in hex formatSudeep Holla2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 90fbee3e4051 ("cmd_fdt: Actually fix fdt command in sandbox") changed the format(from hex address to unsigned long) in which "fdtaddr" is saved . However do_fdt continues reads the "fdtaddr" assuming it to be in hex format. This may lead to fdt being either loaded or attempted to load at erroneous address generating fault if the address is out of memory. This patch changes back the format to hex while saving the "fdtaddr" as it was done before. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Hua Yanghao <huayanghao@gmail.com> Cc: Heiko Schocher <hs@denx.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
* | fdt: armv8: Fix build warnings on armv8Haikun Wang2015-07-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below build warnings on armv8, drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’: drivers/spi/fsl_dspi.c:667:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘fdt_addr_t’ [-Wformat=] debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n", ^ lib/fdtdec.c: In function ‘fdtdec_get_addr_size’: lib/fdtdec.c:105:4: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=] debug("addr=%08lx, size=%08lx\n", ^ Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* | fdt: prevent clearing memory node if there are no banksAndre Przywara2015-07-20-0/+29
|/ | | | | | | | | | | | | Avoid clearing the reg property in the memory DT node if no memory banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0). This allows boards to let U-Boot skip the DT memory tinkering in case other firmware has already setup the node properly before. This should be safe as all callers of fdt_fixup_memory_banks that use a computed <banks> value put at least 1 in there. Add some documentation comments to the header file. Signed-off-by: Andre Przywara <osp@andrep.de> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-15-1623/+2072
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| * pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * pci: Configure expansion ROM during auto config processBin Meng2015-07-14-40/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * drivers: block: Remove the ata_piix driverBin Meng2015-07-14-789/+0
| | | | | | | | | | | | | | | | | | | | | | This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Adjust config option order in defconfig for Crown Bay and MinnowmaxBin Meng2015-07-14-6/+6
| | | | | | | | | | | | | | | | Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig' result so that the config option order matches Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * tools: ifdtool: Write correct offset on 32-bit machineBin Meng2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff, which is wrong for u-boot.rom components like u-boot-x86-16bit.bin. Change to use strtoll() so that it works on both 32-bit and 64-bit machines. Reported-by: Fei Wang <wangfei.jimei@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add binary blob checksums for Minnowboard MAXSimon Glass2015-07-14-0/+8
| | | | | | | | | | | | | | | | | | | | To try to reduce the pain of confusion of binary blobs, add MD5 checksums for the current versions. This may worsen the situation as new versions appear, but it should still be possible to obtain these versions, and thus get a working setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+9
| | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: x86: minnowmax: Move PCI to use driver modelSimon Glass2015-07-14-47/+12
| | | | | | | | | | | | | | | | | | Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-14-27/+8
| | | | | | | | | | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add ROM image description for minnowmaxSimon Glass2015-07-14-0/+17
| | | | | | | | | | | | | | | | The layout of the ROM is a bit hard to discover by reading the code. Add a table to make it easier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: spi: Enable environment for minnowmaxSimon Glass2015-07-14-3/+2
| | | | | | | | | | | | | | | | Enable a SPI environment and store it in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * dm: spi: Correct BIOS protection logic for ICH9Simon Glass2015-07-14-5/+4
| | | | | | | | | | | | | | | | | | The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
| * dm: spi: Correct status register access widthSimon Glass2015-07-14-1/+5
| | | | | | | | | | | | | | | | | | The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-2/+33
| | | | | | | | | | | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| * x86: crownbay: Enable graphics supportBin Meng2015-07-14-14/+23
| | | | | | | | | | | | | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Remove MARK_GRAPHICS_MEM_WRCOMBBin Meng2015-07-14-10/+0
| | | | | | | | | | | | | | | | MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-11/+30
| | | | | | | | | | | | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: cmd_mtrr: Improve MTRR list informationBin Meng2015-07-14-1/+2
| | | | | | | | | | | | | | | | Print the meaningful base address and mask of an MTRR range without showing the memory type encoding or valid bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-10 08:33:24 +0000