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* SMC1 uses external CLK4 instead of BRG on spc1920Markus Klotzbuecher2007-01-09-3/+12
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* Update the SPC1920 CMB PLD driverMarkus Klotzbuecher2007-01-09-10/+8
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* Add / enable I2C support on the spc1920 boardMarkus Klotzbuecher2007-01-09-3/+25
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* Add support for the tms320671x host port interface (HPI)Markus Klotzbuecher2007-01-09-2/+678
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* Prepare for release 1.2.0Wolfgang Denk2007-01-07-4/+125
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* [PATCH] 44x: Fix problem with DDR controller setup (refresh rate)Stefan Roese2007-01-06-1/+1
| | | | | | | This patch fixes a problem with an incorrect setup for the refresh timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update ALPR board filesStefan Roese2007-01-06-21/+29
| | | | | | | This update brings the ALPR board support to the newest version. It also fixes a problem with the NAND driver. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] nand: Fix problem with oobsize calculationStefan Roese2007-01-05-1/+1
| | | | | | | | | | | | | | | | | | Here the description from Brian Brelsford <Brian_Brelsford@dell.com>: The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part returns a 0x15. In the code fragment below bits [1:0] determine the page size, it is ANDed via "(extid & 0x3)" then shifted out. The next field is also ANDed with 0x3. However this is a one bit field as defined in the Hynix and Samsung parts in the 4th ID byte that determins the oobsize, not a two bit field. It works on Samsung as bits[3:2] are 01. However for the Hynix there is a 11 in these two bits, so the oob size gets messed up. I checked the correct linux code and the suggested fix from Brian is also available in the linux nand mtd driver. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-01-05-12/+16
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| * Merge with /home/tur/proj/v38b/u-bootWolfgang Denk2007-01-04-12/+16
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| | * Few V38B changes:Bartlomiej Sieka2006-12-28-12/+16
| | | | | | | | | | | | | | | | | | - fix a typo in V38B config file - move watchdog initialisation earlier in the boot process - add "wdt=off" to default kernel command line (disables kernel watchdog)
* | | [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)Stefan Roese2007-01-05-12/+23
| | | | | | | | | | | | | | | | | | | | | This fix will make the MAL burst disabling patch for the Linux EMAC driver obsolete. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-14/+872
|/ / | | | | | | | | | | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* | Fix bug in adaption of Stefano Babic's CFI driver patch.Wolfgang Denk2006-12-27-15/+21
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* | Minor code cleanup.Wolfgang Denk2006-12-24-328/+322
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* | Merge with /home/wd/git/u-boot/masterWolfgang Denk2006-12-24-1/+3
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| * | Fix cfi failure with Spansion Flash (Spansion Flash Devices have a different ↵Stefano Babic2006-12-24-1/+3
| | | | | | | | | | | | offset to go into CFI mode)
* | | Merge with /home/hs/TQ/u-boot-devWolfgang Denk2006-12-24-16/+2305
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| * | Added support for the TQM8272 board from TQHeiko Schocher2006-12-21-16/+2307
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | [PATCH] Fix sequoia flash autodetection (finally correct)Stefan Roese2006-12-22-3/+11
| | | | | | | | | | | | | | | | | | | | | Now 32MByte and 64MByte FLASH is know to work and other configurations should work too. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Minor code cleanup; update CHANGELOG.Wolfgang Denk2006-12-22-22/+34
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* | | Fix to make the baudrate changes immediate for the MCF52x2 family.Bartlomiej Sieka2006-12-20-1/+1
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* | | Preliminary support for the iDMR board (ColdFire).Bartlomiej Sieka2006-12-20-3/+951
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* | | automatic update mechanismAndrei Safronov2006-12-08-2/+478
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* | | Code cleanup.Wolfgang Denk2006-11-30-1296/+1725
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* | | Merge with http://opensource.freescale.com/pub/scm/u-boot-83xx.gitWolfgang Denk2006-11-30-1647/+11314
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| * | | Make fsl-i2c not conflict with SOFT I2CJoakim Tjernlund2006-11-29-11/+10
| | | | | | | | | | | | | | | | Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | Fix I2C master address initialization.Joakim Tjernlund2006-11-29-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | Merge http://www.denx.de/git/u-bootKim Phillips2006-11-28-219/+2368
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| * | | | Assign maintainers for mpc8349emds and mpc8360emdsKim Phillips2006-11-28-0/+8
| | | | | | | | | | | | | | | | | | | | Dave for mpc8360emds, and me for mpc8349emds.
| * | | | Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.cKim Phillips2006-11-28-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src since they are passed by reference to ucc_get_cmxucr_reg and assigned.
| * | | | mpc83xx: Miscellaneous code style fixesTimur Tabi2006-11-28-218/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement various code style fixes and similar changes. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | mpc83xx: Update 83xx to use fsl_i2c.cTimur Tabi2006-11-03-620/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-82/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | mpc83xx: Lindent and clean up cpu/mpc83xx/speed.cKim Phillips2006-11-03-79/+82
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| * | | | mpc83xx: Fix the incorrect dcbz operationDave Liu2006-11-03-34/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | | | mpc83xx: add OF_FLAT_TREE bits to 83xx boardsKim Phillips2006-11-03-20/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and STDOUT_PATH configuration bits to mpc8349emds, mpc8349itx, and mpc8360emds board code. redo environment to use bootm with the fdtaddr for booting ARCH=powerpc kernels by default, and provide default fdtaddr values.
| * | | | mpc83xx: change ft code to modify local-mac-address propertyKim Phillips2006-11-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Update 83xx OF code to update local-mac-address properties for ethernet instead of the obsolete 'address' property.
| * | | | mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and ↵Timur Tabi2006-11-03-109/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8360EMDS This patch also adds an improved I2C set_speed(), which handles all clock frequencies. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | mpc83xx: add the README.mpc8360emdsDave Liu2006-11-03-0/+126
| | | | | | | | | | | | | | | | | | | | add doc/README.mpc8360emds to accompany the new board support
| * | | | mpc83xx: add QE ethernet supportDave Liu2006-11-03-7/+4138
| | | | | | | | | | | | | | | | | | | | this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
| * | | | mpc83xx: Add MPC8360EMDS basic board supportDave Liu2006-11-03-276/+2092
| | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
| * | | | mpc83xx: add the QUICC Engine (QE) immap fileDave Liu2006-11-03-0/+550
| | | | | | | | | | | | | | | | | | | | common QE immap file. Also required for 8360.
| * | | | mpc83xx: Add 8360 specifics to 83xx immapDave Liu2006-11-03-571/+1404
| | | | | | | | | | | | | | | | | | | | | | | | | Mainly add QE device dependencies, with appropriate 8360 protection. Lindent also run.
| * | | | mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITXTimur Tabi2006-11-03-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2" 2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2" CHANGELOG: * For the 8349E-mITX, fix some size values in pci_init_board(), enable the clock for the 2nd USB board (Linux kernel will hang otherwise), and fix the CONFIG_BOOTARGS macro. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | mpc83xx: Add support for the MPC8349E-mITXTimur Tabi2006-11-03-13/+1926
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | Additional MPC8349 support for multibus i2cBen Warren2006-11-03-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, Here is a patch for a file that was accidentally left out of a previous attempt. It accompanies the patch with ticket DNX#2006090742000024 CHANGELOG: Change PCI initialization to use new multi-bus I2C API. regards, Ben
| * | | | Multi-bus I2C implementation of MPC834xBen Warren2006-11-03-35/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, Attached is a patch implementing multiple I2C buses on the MPC834x CPU family and the MPC8349EMDS board in particular. This patch requires Patch 1 (Add support for multiple I2C buses). Testing was performed on a 533MHz board. /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ Signed-off-by: Ben Warren <bwarren@qstreams.com> CHANGELOG: Implemented driver-level code to support two I2C buses on the MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds are 50kHz, 100kHz and 400kHz on each bus. regards, Ben
| * | | | Add support for multiple I2C busesBen Warren2006-11-03-6/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, Attached is a patch providing support for multiple I2C buses at the command level. The second part of the patch includes an implementation for the MPC834x CPU and MPC8349EMDS board. /*** Note: This patch replaces ticket DNX#2006083042000018 ***/ Signed-off-by: Ben Warren <bwarren@qstreams.com> Overview: 1. Include new 'i2c' command (based on USB implementation) using CONFIG_I2C_CMD_TREE. 2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that the commands to change bus number and speed are only available under the new 'i2c' command mentioned in the first bullet. 3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form of an array of bus-device pairs. Otherwise, it is an array of uchar. CHANGELOG: Added new 'i2c' master command for all I2C interaction. This is conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for setting I2C bus speed as well as changing the active bus if the board has more than one (conditionally compiled with CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses. Updated README. regards, Ben
| * | | | mpc83xx: Add support for Errata DDR6 on MPC 834x systemsTimur Tabi2006-11-03-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CHANGELOG: * Errata DDR6, which affects all current MPC 834x processors, lists changes required to maintain compatibility with various types of DDR memory. This patch implements those changes. Signed-off-by: Timur Tabi <timur@freescale.com>
generated by cgit v1.1 at 2024-11-14 15:27:14 +0000