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* mmc: rockchip: add SDHCI driver support for rockchip socKever Yang2016-07-25-0/+100
| | | | | | | | | | | | | | | | | | Rockchip rk3399 using arasan sdhci-5.1 controller. This patch add the controller support to enable mmc device with full driver-model support, tested on rk3399 evb board. According to my test result, this driver should be OK, the command "part list mmc 0" can result in a right output, but all the mmc command failed like this: => mmc info No MMC device available Command failed, result=1 The result of get_mmc_num in cmd/mmc.c is always 0? Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM64: evb-rk3399: add a README for this board setupKever Yang2016-07-25-0/+73
| | | | | | | | Add a README to guide people flash the ATF and U-Boot with Rockchip tools to bring up to board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* config: add config file for evb-rk3399Kever Yang2016-07-25-0/+33
| | | | | | | This patch add basic config option for evb-rk3399 board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM64: rockchip: add support for rk3399 SoC based evbKever Yang2016-07-25-4/+226
| | | | | | | | | | | RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* dts: add support for Rockchip rk3399 socKever Yang2016-07-25-1/+1880
| | | | | | | | | | | These files are from kernel upstream: "649a371 Add linux-next specific files for 20160616" with some modification need by U-Boot: - chosen with stdout-path to uart2. - add clock-frequency for uart2 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: update fastboot usageXu Ziyuan2016-07-25-0/+26
| | | | | | | Introduce how to use fastboot feature on rk3288. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* mkimage: rockchip: add suport for rk33 serialKever Yang2016-07-25-1/+1
| | | | | | | Add support for rockchip rk33 series Soc like rk3368 and rk3399 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Use rockchip_get_clk() to obtain the SoC clockSimon Glass2016-07-25-5/+5
| | | | | | | | | | | | The current code picks the first available clock. In U-Boot proper this is the oscillator device, not the SoC clock device. As a result the HDMI display does not work. Fix this by calling rockchip_get_clk() instead. Fixes: 135aa950 (clk: convert API to match reset/mailbox style) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* rockchip: Add a way to obtain the main clock deviceSimon Glass2016-07-25-0/+20
| | | | | | | | On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add a way to find a device by its driverSimon Glass2016-07-25-0/+42
| | | | | | | | | Some SoCs have a single clock device. Provide a way to find it given its driver name. This is handled by the linker so will fail if the name is not found, avoiding strange errors when names change and do not match. It is also faster than a string comparison. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: fix FREF_MIN_HZ constantHeiko Stübner2016-07-25-1/+1
| | | | | | | | According to the TRM the minimum FREF frequency is 269kHz not MHz. Adapt the constant accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3288: rename rkclk_configure_cpuHeiko Stübner2016-07-25-3/+3
| | | | | | | | | | The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: sort socs according to numbersHeiko Stübner2016-07-25-21/+21
| | | | | | | | | | Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3036: pinctrl: fix config symbol namingHeiko Stübner2016-07-25-6/+6
| | | | | | | | | Rockchip socs are always named rkxxxx in all places, as also shown by the naming of the rk3036 pinctrl file itself. Therefore also name the config symbol according to this scheme. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3288: pinctrl: fix config symbol namingHeiko Stübner2016-07-25-9/+9
| | | | | | | | The rk3288 pinctrl is very specific to this soc, so should not hog the generic rockchip naming. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: add fastboot supportXu Ziyuan2016-07-25-0/+99
| | | | | | | | | | | | Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* usb: dwc2 : invalidate dcache before starting DMAXu Ziyuan2016-07-25-0/+3
| | | | | | | | | | | | Invalidate dcache before starting the DMA to ensure coherency. In case there are any dirty lines from the DMA buffer in the cache, subsequent cache-line replacements may corrupt the buffer in memory while the DMA is still going on. Cache-line replacement can happen if the CPU tries to bring some other memory locations into the cache while the DMA is going on. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* usb: dwc2-otg: adjust fifo size via platform dataXu Ziyuan2016-07-25-9/+22
| | | | | | | | The total FIFO size of some SoCs may be different from the existen, this patch supports fifo size setting from platform data. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* usb: rockchip-phy: implement USB2.0 phy controlXu Ziyuan2016-07-25-0/+110
| | | | | | | | | So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and Innosilicon. This patch applys dwc2 usb driver framework to implement phy_init() and phy_off() methods for Synopsys phy on Rockchip platform. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Exclude rk_timer for ARM64Andreas Färber2016-07-25-0/+2
| | | | | | | | It conflicts with the generic_timer. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* mkimage: rockchip: add suport for rk33 serialKever Yang2016-07-25-0/+1
| | | | | | | Add support for rockchip rk33 series Soc like rk3368 and rk3399 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Clean up CPU selectionAndreas Färber2016-07-25-1/+2
| | | | | | | | | In preparation for RK3368 and RK3399, which need to select ARM64, don't select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* board: move all the rockchip board in one folderKever Yang2016-07-25-4/+4
| | | | | | | | | | | The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them to 'rockchip' which is a real _vendor_ name, and meet the architecure 'board/<vendor>/<board-name>/'. More boards from rockchip like evb_rk3288, evb_rk3399 will comes later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>
* rockchip: add basic support for evb-rk3288 boardXu Ziyuan2016-07-25-2/+589
| | | | | | | | | | | | | | evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: add option to change method of loading u-bootXu Ziyuan2016-07-25-3/+66
| | | | | | | | | | | | | | | | | If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
* Prepare v2016.09-rc1Tom Rini2016-07-25-2/+2
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* sandbox: Migrate CONFIG_I2C_EEPROMTom Rini2016-07-25-1/+1
| | | | | | | | | Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago, but sandbox was skipped. Leave it off for sandbox_spl where it does not build, but does not need to be either. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-07-25-13/+2057
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| * mtd: fix compiler warningsSteve Rae2016-07-24-2/+7
| | | | | | | | | | | | | | - add missing declaration - update debug output format specifiers Signed-off-by: Steve Rae <steve.rae@raedomain.com>
| * mtd: nand: fix bug writing 1 byte less than page sizeHector Palacios2016-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_do_write_ops() determines if it is writing a partial page with the formula: part_pagewr = (column || writelen < (mtd->writesize - 1)) When 'writelen' is exactly 1 byte less than the NAND page size the formula equates to zero, so the code doesn't process it as a partial write, although it should. As a consequence the function remains in the while(1) loop with 'writelen' becoming 0xffffffff and iterating until the watchdog timeout triggers. To reproduce the issue on a NAND with 2K page (0x800): => nand erase.part <partition> => nand write $loadaddr <partition> 7ff Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * sunxi: Enable NAND controller on the CHIPBoris Brezillon2016-07-24-0/+44
| | | | | | | | | | | | | | Enable the NAND controller in the sun5i-r8-chip.dts. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: nand: Increase CONFIG_SYS_NAND_MAX_ECCPOS valueBoris Brezillon2016-07-24-0/+1
| | | | | | | | | | | | | | On some sunxi boards we have NANDs exposing 1664 OOB bytes per page. Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * mtd: nand: Increase the max OOB sizeBoris Brezillon2016-07-24-1/+1
| | | | | | | | | | | | | | Some NANDs are now exposing 1664 OOB bytes per page. Adjust the NAND_MAX_OOBSIZE value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NANDBoris Brezillon2016-07-24-0/+4
| | | | | | | | | | | | | | Add a full-id entry for the H27QCG8T2E5R‐BCF NAND. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sun5i: Add NAND controller to the sun5i DTSIMaxime Ripard2016-07-24-0/+49
| | | | | | | | | | | | | | Add the NAND controller definition to sun5i.dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * mtd: nand: Add the sunxi NAND controller driverBoris Brezillon2016-07-24-4/+1862
| | | | | | | | | | | | | | | | | | | | | | We already have an SPL driver for the sunxi NAND controller, now add the normal/standard one. The source has been copied from Linux 4.6 with a few changes to make it work in u-boot. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * mtd: nand: add common DT init codeBrian Norris2016-07-24-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are already-documented common bindings for NAND chips. Let's handle them in nand_base. If NAND controller drivers need to act on this data before bringing up the NAND chip (e.g., fill out ECC callback functions, change HW modes, etc.), then they can do so between calling nand_scan_ident() and nand_scan_tail(). The original commit has been slightly reworked to use the fdtdec_xxx() helpers (instead of the of_xxxx() ones). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add missing macros to configure the NAND controller clkBoris Brezillon2016-07-24-0/+5
| | | | | | | | | | | | | | We need some macros to manipulate the NAND controller clock. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * cmd, nand: add an option to disable the verification when writing in raw modeBoris Brezillon2016-07-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern NANDs do not guarantee that data written in raw mode will not contain bitflips just after writing them. This is fine since the number of bitflips should be rather low and thus fixable by the ECC engine, but since we are reading data in raw mode to verify if they match the input data we cannot prevent failures if some bits are flipped. The option of using standard mode to verify the data is not acceptable either, since one of the usage of raw mode is to allow flashing images that do not respect the standard NAND page layout or the default ECC config (this is the case on Allwinner platforms, where the ROM code tests several hardcoded configs, which are not necessarily matching the NAND characteristics). Add an extension to the nand write.raw command allowing one to disable the verification step. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: thunderx_88xx_defconfig: remove unneeded CONFIG_SYS_EXTRA_OPTIONSMasahiro Yamada2016-07-25-1/+0
| | | | | | | | | | | | | | | | ARM64 is correctly select'ed in arch/arm/Kconfig, so this line in the defconfig is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | dtoc: Correct the type widening code in fdt_fallbackSimon Glass2016-07-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This code does not match the fdt version in fdt.py. When dtoc is unable to use the Python libfdt library, it uses the fallback version, which does not widen arrays correctly. Fix this to avoid a warning 'excess elements in array initialize' in dt-platdata.c which happens on some platforms. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com>
* | hashtable: Fix compiler warning on 32-bit sandboxSimon Glass2016-07-25-5/+5
| | | | | | | | | | | | | | This fixes a mismatch between the %zu format and the type used on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | part_efi: Fix compiler warning on 32-bit sandboxSimon Glass2016-07-25-5/+5
| | | | | | | | | | | | | | This fixes a mismatch between the %zu format and the type used on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | lzmadec: Use the same type as the lzma callSimon Glass2016-07-25-2/+3
| | | | | | | | | | | | | | | | With sandbox on 32-bit the size_t type can be a little inconsistent. Use the same type as the caller expects to avoid a compiler warning. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sandbox: Add instructions about building on 32-bit machinesSimon Glass2016-07-25-1/+7
| | | | | | | | | | | | | | | | Sandbox is built with 64-bit ints by default. This doesn't work properly on 32-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | tools, rsa: Further minor cleanups on top of c236ebd and 2b9ec7mario.six@gdsys.cc2016-07-25-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [NOTE: I took v1 of these patches in, and then v2 came out, this commit is squashing the minor deltas from v1 -> v2 of updates to c236ebd and 2b9ec76 into this commit - trini] - Added an additional NULL check, as suggested by Simon Glass to fit_image_process_sig - Re-formatted the comment blocks Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> [For merging the chnages from v2 back onto v1] Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: am33xx: Always inhibit init/refresh during DDR phy initRuss Dill2016-07-25-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of commits have modified the am33xx/am437x ddr2/ddr3 initialization path to fix certain issues, but have had the side effect of causing L3 noc errors during initialization. The two commits are: 69b918 "am33xx,ddr3: fix ddr3 sdram configuration" fc46ba "arm: am437x: Enable hardware leveling for EMIF" The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all platforms. This delays initialization and refresh until a later stage. The 500us timer can be programmed for platforms that require it and for platforms that don't require it. It is currently hardcoded for 400MHz systems. For systems with a higher memory frequency this needs to be a larger value, and for systems with a lower memory frequency this can be a lower value. This can be considered a separate issue and corrected in a later commit. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: am33xx: Fix DDR init delay placementRuss Dill2016-07-25-1/+4
| | | | | | | | | | | | | | | | | | The delay needs to be before the write to ref_ctrl register which initiates refreshes. An improper initialization sequence generates an L3 noc error. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | efi_loader: Make exposed image loader path absoluteAlexander Graf2016-07-25-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | When loading an efi image, we pass it the location it was loaded from. On file system backends, there are no relative paths, so we should always pass in absolute ones. For network paths, we may be relative. This fixes distro booting with grub2 for me when it fetches the grub2 config file from the loader partition. Reported-by: york sun <york.sun@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | common: fit: Allow U-Boot images to be bootedmario.six@gdsys.cc2016-07-25-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In certain circumstances it comes in handy to be able to boot into a second U-Boot. But as of now it is not possible to boot a U-Boot binary that is inside a FIT image, which is problematic for projects that e.g. need to guarantee a unbroken chain of trust from SOC all the way into the OS, since the FIT signing mechanism cannot be used. This patch adds the capability to load such FIT images. An example .its snippet (utilizing signature verification) might look like the following: images { firmware@1 { description = "2nd stage U-Boot image"; data = /incbin/("u-boot-dtb.img.gz"); type = "firmware"; arch = "arm"; os = "u-boot"; compression = "gzip"; load = <0x8FFFC0>; entry = <0x900000>; signature@1 { algo = "sha256,rsa4096"; key-name-hint = "key"; }; }; }; Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-09 22:21:15 +0000