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* zynq: defconfig: Remove unnecessary board specific config filesSiva Durga Prasad Paladugu2016-07-22-67/+7
| | | | | | | | | Remove unnecessary board specifc config files for zynq boards(microzed, picozed, ZC770(all), zed) and point to zynq common config file. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: config: Enable CONFIG_SYS_NO_FLASH through defconfigSiva Durga Prasad Paladugu2016-07-22-17/+9
| | | | | | | | Enable config CONFIG_SYS_NO_FLASH through defconfig for all zynq boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Kconfig: Move option CONFIG_SYS_NO_FLASH to KconfigSiva Durga Prasad Paladugu2016-07-22-0/+6
| | | | | | | | | Move config option CONFIG_SYS_NO_FLASH as Kconfig option. All the boards which needs to enable this option can be done through defconfigs Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* usb: zynq: Define config USB_STORAGE through defconfigSiva Durga Prasad Paladugu2016-07-22-1/+6
| | | | | | | | Define config USB_STORAGE through defconfig for all respective zynq boards Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQSiva Durga Prasad Paladugu2016-07-22-11/+20
| | | | | | | | | Add Kconfig entry config option for USB_EHCI_ZYNQ and update the same to enable for all zynq boards which supports USB Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable AHCI on EP platformAlexander Graf2016-07-22-0/+1
| | | | | | | | The EP platform also has working AHCI emulation, so I see little reason not to implement the plumbing for it that enables us to boot from AHCI. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Remove empty ifdef around cachesMichal Simek2016-07-22-4/+0
| | | | | | Code around was removed because of move to Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: clk: Remove simple version of clk_get_by_index/name()Michal Simek2016-07-22-27/+1
| | | | | | | | | | | | | | | | Simple version of clk_get_by_index() added by: "dm: clk: Add a simple version of clk_get_by_index()" (sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44) is only working for #clock-cells=<1> but not for any other values. Fixed clocks is using #clock-cells=<0> which requires full implementation. Remove simplified versions of clk_get_by_index() and use full version. Also remove empty clk_get_by_name() which is failing when it is called which is useless. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* ARM64: zynqmp: Remove get_uart_clk()Michal Simek2016-07-22-17/+0
| | | | | | ZynqMP will use reading clock freq directly from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* serial: zynq: Read information about clock from DTMichal Simek2016-07-22-1/+27
| | | | | | | | Read information about clock frequency from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* ARM64: zynqmp: Enable SPL for all zynqmp boardsMichal Simek2016-07-22-0/+35
| | | | | | | Compile SPL for all boards even psu_init.c/h files are not in the tree yet. But this change enables covering SPL issues in mainline. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable CLK and SPL_CLK by defaultMichal Simek2016-07-22-14/+2
| | | | | | | Serial driver starts to use clk framework that's why enable it by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spl: Fix compilation warnings for arm64Michal Simek2016-07-22-2/+3
| | | | | | | | | | | | | | | Make code 64bit aware. Warnings: +../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’: +../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +../common/spl/spl_fat.c: In function ‘spl_load_image_fat’: +../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: sdhci: Disable internal clock enable bitSiva Durga Prasad Paladugu2016-07-22-1/+1
| | | | | | | | | | | Disable internal clock by clearing the internal clock enable bit. This bit needs to be cleared too when we stop the SDCLK for changing the frequency divisor. This bit should be set to zero when the device is not using the Host controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* api: Disable api_net when DM is usedMichal Simek2016-07-22-1/+1
| | | | | | | | | | | | | | | | | When CONFIG_API is selected with DM_ETH this error is present: api/api_net.c: In function 'dev_enum_net': api/api_net.c:61:35: warning: initialization from incompatible pointer type struct eth_device *eth_current = eth_get_dev(); ^ api/api_net.c:68:39: error: dereferencing pointer to incomplete type memcpy(di->di_net.hwaddr, eth_current->enetaddr, 6); ^ Disable api_net functions when ETH_DM is selected. Signed-off-by: Chris Johns <chrisj@rtems.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq/zynqmp: Use the default CONFIG_BOOTDELAY=2Michal Simek2016-07-22-17/+0
| | | | | | | | | | | | Based on: "ARM: uniphier: use the default CONFIG_BOOTDELAY=2" (sha1: 7c8ef0feb97586d35b0296b48903daef8c06ab21) "I do not insist on CONFIG_BOOTDELAY=3. The default value in Kconfig, CONFIG_BOOTDELAY=2, is just fine for these boards." Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"Tom Rini2016-07-21-11/+7
| | | | | | | | | | Per Vikas' request, the problem this commit is supposed to be solving is something he doesn't see and further this introduces additional hardware requirements. This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440. Signed-off-by: Tom Rini <trini@konsulko.com>
* image: fix IH_ARCH_... values for uImage compatibilityMasahiro Yamada2016-07-21-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 555f45d8f916 ("image: Convert the IH_... values to enums") accidentally changed some IH_ARCH_... values. Prior to that commit, there existed a gap between IH_ARCH_M68K and IH_ARCH_MICROBLAZE, like follows. #define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ #define IH_ARCH_M68K 12 /* M68K */ #define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ #define IH_ARCH_NIOS2 15 /* Nios-II */ The enum conversion broke the compatibility with existing uImage files. Reverting 555f45d8f916 will cause build error unfortunately, so here is a more easy fix. I dug the git history and figured out the gap was introduced by commit 1117cbf2adac ("nios: remove nios-32 arch"). So, I revived IH_ARCH_NIOS just for filling the gap. I added comments to each enum block. Once we assign a value to IH_... it is not allowed to change it. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2016-07-21-0/+37
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| * serial_sh: Add standrad SCI (w/o FIFO) supportYoshinori Sato2016-07-09-1/+4
| | | | | | | | | | | | | | Add support for standard type SCI (without FIFO) port. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * serial_sh: Device Tree supportYoshinori Sato2016-07-09-0/+34
| | | | | | | | | | | | | | Add Device Tree bindings. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | mtd: cfi_flash: fix polling for bit XSR.7 on Intel chipsDaniel Schwierzeck2016-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash_full_status_check() checks bit XSR.7 on Intel chips. This should be done by only checking bit 7 and not by comparing the whole status byte or word with 0x80. This fixes the non-working block erase in the pflash emulation of Qemu when used with the MIPS Malta board. MIPS Malta uses x32 mode to access the pflash device. In x32 mode Qemu mirrors the lower 16 bits of the status word into the upper 16 bits. Thus the CFI driver gets a status word of 0x8080 in x32 mode. If flash_full_status_check() uses flash_isequal(), then it polls for XSR.7 by comparing 0x8080 with 0x80 which never becomes true. Reported-by: Alon Bar-Lev <alon.barlev@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-646/+1084
|\ \ | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * | ARMv8/ls1043ardb: Integrate FSL PPAHou Zhiqiang2016-07-19-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PPA use PSCI to make secondary cores bootup. So when PPA was enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method between PSCI and spin-table. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8/PSCI: Fixup the device tree for PSCIHou Zhiqiang2016-07-19-64/+159
| | | | | | | | | | | | | | | | | | | | | | | | Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8/Layerscape: switch SMP method accordinglyHou Zhiqiang2016-07-19-3/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8/layerscape: Add FSL PPA supportHou Zhiqiang2016-07-19-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FSL Primary Protected Application (PPA) is a software component loaded during boot which runs in TrustZone and remains resident after boot. Use the secure firmware framework to integrate FSL PPA into U-Boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8: add the secure monitor firmware frameworkHou Zhiqiang2016-07-19-0/+342
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This framework is introduced for ARMv8 secure monitor mode firmware. The main functions of the framework are, on EL3, verify the firmware, load it to the secure memory and jump into it, and while it returned to U-Boot, do some necessary setups at the 'target exception level' that is determined by the respective secure firmware. So far, the framework support only FIT format image, and need to define the name of which config node should be used in 'configurations' and the name of property for the raw secure firmware image in that config. The FIT image should be stored in Byte accessing memory, such as NOR Flash, or else it should be copied to main memory to use this framework. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: add i/d-cache enable function to enable_cachesHou Zhiqiang2016-07-19-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Convert to use common MMU frameworkYork Sun2016-07-19-432/+238
| | | | | | | | | | | | | | | | | | | | | | | | Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: mmu: Add support of non-identical mappingYork Sun2016-07-15-53/+86
| | | | | | | | | | | | | | | | | | | | | Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: mmu: split block if necessaryYork Sun2016-07-15-32/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | When page tables are created, allow later table to be created on previous block entry. Splitting block feature is already working with current code. This patch only rearranges the code order and adds one condition to call split_block(). Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: mmu: house cleaningYork Sun2016-07-15-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | Make setup_pgtages() and get_tcr() available for platform code to customize MMU tables. Remove unintentional call of create_table(). Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: Add tlb_allocated to arch global dataYork Sun2016-07-15-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | When secure ram is used, MMU tables have to be put into secure ram. To use common MMU code, gd->arch.tlb_addr will be used to host TLB entry pointer. To save allocated memory for later use, tlb_allocated variable is added to global data structure. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-63/+69
| | | | | | | | | | | | | | | | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
* | | test: Adjust the of-platdata test run conditionSimon Glass2016-07-16-1/+1
| | | | | | | | | | | | | | | | | | | | | This should be spl_of_platdata, since otherwise it will try to run on boards that don't support of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | | configs: Add more CONFIG_ARMV7_PSCI_NR_CPUS entriesTom Rini2016-07-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code had assumed 4 CPUS before and now we have this configurable. For now, set this to the previous default. Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-334/+1716
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| * | | ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.SChen-Yu Tsai2016-07-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a secure data section for storing variables, there should be no need for platform code to get the stack address. Make psci_get_cpu_stack_top a local function, as it should only be used in armv7/psci.S and only by psci_stack_setup. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: PSCI: Switch to per-CPU target PC storage in secure data sectionChen-Yu Tsai2016-07-15-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a secure data section and space to store per-CPU target PC address, switch to it instead of storing the target PC on the stack. Also save clobbered r4-r7 registers on the stack and restore them on return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: PSCI: Add helper functions to access per-CPU target PC storageChen-Yu Tsai2016-07-15-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a data section, add helper functions to save and fetch per-CPU target PC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: Add secure section for initialized dataChen-Yu Tsai2016-07-15-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The secure monitor may need to store global or static values within the secure section of memory, such as target PC or CPU power status. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: Move __secure definition to common asm/secure.hChen-Yu Tsai2016-07-15-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sunxi and i.mx7 both define the __secure modifier to put functions in the secure section. Move this to a common place. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Define CONFIG_ARMV7_SECURE_MAX_SIZE for sun6i/sun7iChen-Yu Tsai2016-07-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Both sun6i and sun7i have 64 KB of secure SRAM. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: Add CONFIG_ARMV7_SECURE_MAX_SIZE and check size of secure sectionChen-Yu Tsai2016-07-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the PSCI implementation grows, we might exceed the size of the secure memory that holds the firmware. Add a configurable CONFIG_ARMV7_SECURE_MAX_SIZE so platforms can define how much secure memory is available. The linker then checks the size of the whole secure section against this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: PSCI: Remove unused psci_text_end symbolChen-Yu Tsai2016-07-15-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | psci_text_end was used to calculate the PSCI stack address following the secure monitor text. Now that we have an explicit secure stack section, this is no longer used. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: PSCI: Allocate PSCI stack in secure stack sectionChen-Yu Tsai2016-07-15-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a secure stack section that guarantees usable memory, allocate the PSCI stacks in that section. Also add a diagram detailing how the stacks are placed in memory. Reserved space for the target PC remains unchanged. This should be moved to global variables within a secure data section in the future. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: Add an empty secure stack sectionChen-Yu Tsai2016-07-15-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now we've been using memory beyond psci_text_end as stack space for the secure monitor or PSCI implementation, even if space was not allocated for it. This was partially fixed in ("ARM: allocate extra space for PSCI stack in secure section during link phase"). However, calculating stack space from psci_text_end in one place, while allocating the space in another is error prone. This patch adds a separate empty secure stack section, with space for CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also __secure_stack_start and __secure_stack_end symbols. The linker script handles calculating the correct VMAs for the stack section. For platforms that relocate/copy the secure monitor before using it, the space is not allocated in the executable, saving space. For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page of stack space for 4 CPUs is allocated, matching the previous behavior. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: PSCI: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for PSCI enabled platformsChen-Yu Tsai2016-07-15-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original PSCI implementation assumed CONFIG_ARMV7_PSCI_NR_CPUS=4. Add this to platforms that have not defined it, using CONFIG_MAX_CPUS if it is defined, or the actual number of cores for the given platform. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
generated by cgit v1.1 at 2024-11-09 22:23:48 +0000