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* spi: tegra: Use GENMASKJagan Teki2015-10-27-9/+9
| | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in tegra*.c Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: omap3_spi: Use GENMASKJagan Teki2015-10-27-5/+5
| | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in omap3_spi Cc: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: fsl_qspi: Use GENMASKJagan Teki2015-10-27-1/+1
| | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in fsl_qspi Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: designware_spi: Use GENMASKJagan Teki2015-10-27-1/+1
| | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in designware_spi Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: atmel_spi: Use GENMASKJagan Teki2015-10-27-1/+1
| | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in atmel_spi Cc: Bo Shen <voice.shen@atmel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: xilinx_spi: Use BIT macroJagan Teki2015-10-27-16/+16
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in xilinx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Use BIT macroJagan Teki2015-10-27-5/+5
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in ti_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: tegra: Use BIT macroJagan Teki2015-10-27-86/+86
| | | | | | | | | | | | | Replace numerical bit shift with BIT macro in tegra*.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: sh_qspi: Use BIT macroJagan Teki2015-10-27-8/+8
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in sh_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: omap3_spi: Use BIT macroJagan Teki2015-10-27-24/+24
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in omap3_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: mpc8xxx_spi: Use BIT macroJagan Teki2015-10-27-1/+1
| | | | | | | | | | | Replace numerical bit shift with BIT macro in mpc8xxx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: ich: Use BIT macroJagan Teki2015-10-27-2/+2
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in ich :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: fsl: Use BIT macroJagan Teki2015-10-27-13/+13
| | | | | | | | | | | | | Replace numerical bit shift with BIT macro in fsl_*spi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: designware_spi: Use BIT macroJagan Teki2015-10-27-7/+7
| | | | | | | | | | | | | Replace numerical bit shift with BIT macro in designware_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: cadence_qspi_apb: Use BIT macroJagan Teki2015-10-27-14/+14
| | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in cadence_qspi_apb :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: bfin_spi6xx: Use BIT macroJagan Teki2015-10-27-4/+4
| | | | | | | | | | | Replace numerical bit shift with BIT macro in bfin_spi6xx :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: atmel_spi: Use BIT macroJagan Teki2015-10-27-26/+26
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in atmel_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Bo Shen <voice.shen@atmel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_[q]spi: Use GENMASK macroJagan Teki2015-10-27-7/+7
| | | | | | | | | | | GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_[q]spi: Use BIT macroJagan Teki2015-10-27-18/+18
| | | | | | | | | | | | Used BIT macro on zynq_spi.c and zynq_qspi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_qspi: Minor cleanupsJagan Teki2015-10-25-5/+3
| | | | | | | | - Use __func__ on debug - Removed unnecessary comment - Fix function name in debug as zynq_qspi_xfer instead of spi_xfer Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Add FSR support to spi_flash_cmd_wait_readyJagan Teki2015-10-25-11/+60
| | | | | | | | | | | | | | | | | This patch adds flag status register reading support to spi_flash_cmd_wait_ready. Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Hou Zhiqiang <B48286@freescale.com> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Update status reg check in spi_flash_cmd_wait_readyJagan Teki2015-10-25-58/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current flash wait_ready logic is not modular to add new register status check, hence updated the status check for adding few more register checks in future. Below are the sf speed runs with 'sf update' on whole flash, 16MiB. => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.564s, speed 289262 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 62.549s, speed 275036 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 61.276s, speed 284359 B/s Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* sf: Make flash->flags use for generic usageJagan Teki2015-10-25-7/+11
| | | | | | | | | | Use the flash->flags for generic usage, not only for dm-spi-flash, this will be used for future flag additions. [Correct the spi flash flags detect logic] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Optimize BAR write codeJagan Teki2015-10-25-28/+13
| | | | | | | | | | Optimized spi-flash bar writing code and also removed unnecessary bank_sel in read_ops. Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Add spi_flash_read_barJagan Teki2015-10-25-19/+34
| | | | | | | | | Add spi_flash_read_bar function for reading bar and discovering bar commands at probe time. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Return bank_sel, if flash->bank_curr == bank_selJagan Teki2015-10-25-1/+1
| | | | | | | | | If computed bank_sel is same as flash->bank_curr which is computed at probe time, then return the bank_sel instead of zero. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_spi: Remove unneeded headersJagan Teki2015-10-25-5/+1
| | | | | | | | | - Removed unneeded inclusion of header files - Add "Xilinx" on license text Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* zynq-common: Add SPL SPI offset, size configsSiva Durga Prasad Paladugu2015-10-25-0/+4
| | | | | | | | | | Define CONFIG_SYS_SPI_ARGS_OFFS, CONFIG_SYS_SPI_ARGS_SIZE and CONFIG_SYS_SPI_KERNEL_OFFS which will be used in SPL spi mode. These macros defines the device tree offset, size and the kernel image offset in flash respectively. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_qspi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-25-3/+4
| | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* zynq-common: Enable ISSI SPI-NOR flash supportJagan Teki2015-10-25-0/+1
| | | | | | | | This patch enabled CONFIG_SPI_FLASH_ISSI for qspi on zynq boards. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
* sf: params: Add IS25LP128 part supportJagan Teki2015-10-25-0/+1
| | | | | | | | Added support for IS25LP128 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
* sf: params: Add IS25LP064 part supportJagan Teki2015-10-25-0/+1
| | | | | | | | Added support for IS25LP064 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
* sf: params: Add IS25LP032 part supportJagan Teki2015-10-25-0/+3
| | | | | | | | Added support for IS25LP032 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
* spi: zynq_spi: Store cs value into private dataJagan Teki2015-10-25-3/+5
| | | | | | | Store cs value into private data and use it while activating chipselect instead of passing through function. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_spi: Rename baudrate divisor mask nameJagan Teki2015-10-25-2/+2
| | | | | | | Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK for more readable. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_spi: Add config reg shift named macrosJagan Teki2015-10-25-3/+7
| | | | | | | Update the numerical values for baudrate and chipselect with config reg shift named macro's Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Kconfig: Add Zynq QSPI controller entryJagan Teki2015-10-25-0/+9
| | | | | | | | | Add Zynq QSPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* configs: zynq: Enable zynq qspi controllerJagan Teki2015-10-25-0/+6
| | | | | | | | | | Enable zynq qspi controller driver on respective zynq boards. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* zynq-common: Enable Bank/Extended address register supportJagan Teki2015-10-25-0/+1
| | | | | | | | | Enabled SPI flash Bank/Extended address register support. Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. Signed-off-by: Jagan Teki <jteki@openedev.com>
* zynq-common: Enable zynq qspi controller supportJagan Teki2015-10-25-0/+9
| | | | | | | | | | | This patch adds support for zynq qspi controller driver on zynq-common.h Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* configs: Enable legacy SPI flash interface supportJagan Teki2015-10-25-0/+5
| | | | | | | | | | | Enable legacy spi-flash interface support for boards which supports qspi controller with connected spi-nor flash. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* dts: zed: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | Enabled zynq qspi controller node for zed board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* dts: zc770-xm010: Enable zynq qspi controller nodeJagan Teki2015-10-25-1/+6
| | | | | | | | | | | | Enabled zynq qspi controller node for zc770-xm010 board. => sf probe 0 -- bus1 for selecting qspi controller => sf probe 1 -- bus0 for selecting spi controller Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* dts: zc706: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | Enabled zynq qspi controller node for zc706 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* dts: zc702: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | Enabled zynq qspi controller node for zc702 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* dts: microzed: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | | | Enabled zynq qspi controller node for microzed board, verified the same on spansion spi-nor flash. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* doc: device-tree-bindings: spi: Add zynq qspi infoJagan Teki2015-10-25-0/+26
| | | | | | | | | | | Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* dts: zynq: Add zynq qspi controller nodesJagan Teki2015-10-25-0/+12
| | | | | | | | | | This patch adds zynq qspi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* spi: Add zynq qspi controller driverJagan Teki2015-10-25-0/+623
| | | | | | | | | | | | | | | | | | | | | | | Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* common/board_f.c: modify the macro to use get_clocks() more commonGong Qianyu2015-10-24-1/+41
| | | | | | get_clocks() should not be limited by ESDHC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
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