summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* net: phy: micrel: Fix error handlingMarek Vasut2016-12-08-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Fix the following error, the $ret variable handling must be part of the loop, while due to the missing parenthesis it was not. drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’: drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’: drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-12-06-0/+81
|\
| * usb: xhci-pci: Add DM supportStefan Roese2016-12-06-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DM support to the xHCI PCI driver. Enabling its use e.g. in x86 platforms. Status: On the congatec BayTrail SoM, xHCI still does not work correctly with this patch. Some internal timeouts lead to resets (BUG). Additional work is needed here. I'm posting this version as WIP so that other developers interested in this support might use it as a start. I might get back to it in a few weeks as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | MAINTAINERS: Fix ALTERA SOCFPGA FilesJagan Teki2016-12-06-2/+1
| | | | | | | | | | | | | | | | | | | | Replace arch/arm/cpu/armv7/socfpga/ path with arch/arm/mach-socfpga/ and removed board file path since board/altera has different boards with relevant board maintainers. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
* | MAINTAINERS: socfpga: update email address for Dinh NguyenDinh Nguyen2016-12-06-4/+5
| | | | | | | | | | | | | | With the acquisition of Altera by Intel, my Altera email may be going away soon. Update the contact to a more reliable address. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | qts-filter.sh: strip DOS line endings and handle continuation linesBill Randle2016-12-06-15/+32
| | | | | | | | | | | | | | | | | | Some Altera Quartus generated files have long lines that are split with a '\' at the end of the line. It also wOn Windows, rites files in DOS format, which can confuse some of the processing scripts in this file. This patch solves both issues. Signed-off-by: Bill Randle <bill.randle@gmail.com> Cc: Marek Vasut <marex@denx.de>
* | ARM: socfpga: Add boot0 hook to prevent SPL corruptionMarek Vasut2016-12-06-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | socfpga: add support for Terasic DE1-SoC boardAnatolij Gustschin2016-12-06-0/+1528
|/ | | | | | | | Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
* Prepare v2017.01-rc1Tom Rini2016-12-05-3/+3
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-12-05-62/+233
|\
| * armv8: QSPI: Add AHB bus 16MB+ size supportYuan Yao2016-12-05-0/+55
| | | | | | | | | | | | | | | | The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/usb: enable the errata-a005697 for ls1012ajerry.huang@nxp.com2016-12-05-0/+4
| | | | | | | | | | | | | | Enable the errata-a005697 for ls1012a Signed-off-by: Changming Huang <jerry.huang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1021a: QSPI: update the node for QSPI supportYuan Yao2016-12-05-0/+1
| | | | | | | | | | | | | | | | | | Add the name for register space and memory space. <0x1550000 0x10000 > is the QSPI register space. <0x40000000 0x4000000> is the QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Add serdes1 protocol 0x3b supportPriyanka Jain2016-12-05-0/+1
| | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu2016-12-05-38/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/ddr: Fix compiling warningShengzhou Liu2016-12-05-32/+25
| | | | | | | | | | | | | | | | | | Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | travis-ci: Build mvebu boards (arm & aarch64) in separate jobStefan Roese2016-12-05-2/+4
| | | | | | | | | | | | | | | | | | | | Its easier to watch the output of the build process when the platforms specific boards are grouped in a separate job. This patch adds a job for all mvebu boards (arm and aarch64). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: increase PLL0 frequencyBartosz Golaszewski2016-12-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LCDC controller on the lcdk board has high memory throughput requirements. Even with the kernel-side tweaks to master peripheral and peripheral bus burst priorities, the default PLL0 frquency of 300 MHz is not enough to service the LCD controller and causes DMA FIFO underflows. Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of 456 MHz - the same value that downstream reference u-boot from Texas Instruments uses. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: baltos: enable booting from USBYegor Yefremov2016-12-05-0/+33
| | | | | | | | | | | | | | | | | | | | | | First of all U-Boot would search for a USB mass storage device with either uEnv.txt or kernel-fit.itb and boot. If USB mass storage device is not available or doesn't provide these files then MMC will be tried. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: baltos: active mPCIe slotYegor Yefremov2016-12-05-0/+18
| | | | | | | | | | | | | | | | | | Baltos devices provide a mPCIe slot, whose power is turned off by default. This patch activates mPCIe slot in U-Boot, so that for example GSM modem can be already available in user space. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: baltos: remove TI board leftoverYegor Yefremov2016-12-05-125/+0
| | | | | | | | | | | | | | Remove unneeded pinmux configurations and TI EEPROM struct. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: AMxx: Make sure that the SPL always reads the configuration EEPROMJean-Jacques Hiblot2016-12-05-4/+6
| | | | | | | | | | | | | | | | | | The bootrom may corrupt the area of SRAM used to store the ti_common_eeprom structure. This patch makes sure that it's always read after a reset, even if a valid MAGIC number is found in the SRAM. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | dm: spl: mmc: Fix EXT SPL supportMichal Simek2016-12-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch "dm: spl: mmc: Support CONFIG_BLK in SPL MMC" (sha1: 87bce4e5c0b55452d70830928b2d7b98fa24d4e3) converted FAT part of spl_mmc_do_fs_boot() but forget to update also EXT part by 's/&mmc->block_dev/mmc_get_blk_desc(mmc)/'. This patch is fixing compilation error when CONFIG_SPL_EXT_SUPPORT is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://www.denx.de/git/u-boot-i2cTom Rini2016-12-05-1242/+752
|\ \ | |/ |/|
| * dm: Add timeline and guide for porting I2C driversSimon Glass2016-12-05-0/+56
| | | | | | | | | | | | | | | | | | | | | | Add a README with a brief guide to porting i2c drivers over to use driver model. Add a timeline also. All I2C drivers should be converted by the end of June 2017. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: i2c: Add a note to I2C drivers which need conversionSimon Glass2016-12-05-0/+42
| | | | | | | | | | | | | | | | Maintainers need to be notified more directly of the need to convert these drivers. Add a note to the top each affected file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * samsung: i2c: Split the high-speed I2C code into a new driverSimon Glass2016-12-05-545/+591
| | | | | | | | | | | | | | | | | | Now that driver model is used for I2C on all boards, we can split the high-speed code into its own driver. There is virtually no common code, and this significantly reduces confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * samsung: i2c: Drop old code from I2C driverSimon Glass2016-12-05-583/+2
| | | | | | | | | | | | | | Now that all boards use DM_I2C we can drop the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * arm: samsung: Convert s5p_goni and smdkc100 to DM_I2CSimon Glass2016-12-05-20/+7
| | | | | | | | | | | | | | | | These are the last two samsung boards that don't use DM_I2C. Move them over, leaving #ifdefs to allow the maintainer to complete this work. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * arm: exynos: i2c: Convert exynos boards to use DM_I2CSimon Glass2016-12-05-94/+54
| | | | | | | | | | | | | | | | | | | | Three boards are still not converting to use DM_I2C. They are also using the old PMIC framework. Rather than removing them, add #ifdefs to allow them to continue to build. This will give the maintainers a little more time to decide whether to convert them or not. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* | sata: sata_mv: Fix misaligned cache warningsStefan Roese2016-12-05-3/+9
| | | | | | | | | | | | | | | | This patch fixes the warnings about misaligned cache on Armada XP: CACHE: Misaligned operation at range [7facb400, 7facb460] Signed-off-by: Stefan Roese <sr@denx.de>
* | arm64: mvebu: Restrict memory size to a usable maximumStefan Roese2016-12-05-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all memory is mapped in the MMU. So we need to restrict the memory size so that U-Boot does not try to access it. Also, the internal registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB are mapped for system memory. This is what we pass to the U-Boot subsystem here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add PCI support to DB-88F8040 boardStefan Roese2016-12-05-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds PCI support to the Marvell Armada-8K devel board. Additionally the Intel E1000 ethernet driver is enabled so that network support is available on this board, even without the internal network interfaces being supported (yet). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add regions for PCI spaces to the memory mapStefan Roese2016-12-05-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To use the PCIe driver, its controller memory and the PCIe regions need to get mapped in the MMU. Otherwise these areas can't be accessed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | pci: mvebu: Add PCIe driver for Armada-8KShadi Ammouri2016-12-05-0/+546
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core. The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support. Tested on the Marvell DB-88F8040 Armada-8K eval board. Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | drivers/phy: marvell: Add support for the slave CP COMPHY deviceStefan Roese2016-12-05-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the support for the Armada 8k, a 2nd COMPHY controller now needs to get supported from the CP110 slave controller. This patch adds support for this 2nd contoller in the COMPHY driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Init COMPHY from the slave-CP on the A8kStefan Roese2016-12-05-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada8k implements 2 CPs (communication processors) and the 2nd CP also is equipped with a COMPHY controller. This patch now loops over all enabled MISC devices (CP110) enabled in the DT to initialize all CPs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: armada-8040-db.dts: Add I2C and SPI aliasesStefan Roese2016-12-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C and SPI aliases to enable usage in U-Boot. Otherwise U-Boot will not be able to use the SPI NOR chip for environment storage and use "i2c dev 0" to select this I2C bus. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: armada-8040-db.dts: Add COMPHY configurationStefan Roese2016-12-05-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the COMPHY device tree configuration to the DT file for the Marvell DB-88F8040 devel board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: armada-cp110-slave.dtsi: Add COMPHY / UTMI device tree nodesStefan Roese2016-12-05-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the COMPHY and UTMI device tree nodes to the cp110-slave dtsi file for the Armada 8K. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: armada-cp110-master.dtsi: Rename comphy DT node namesStefan Roese2016-12-05-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the cp110 slave also has comphy DT nodes, the names need to be renamed to avoid a name clash. Lets use the common naming scheme: "cpm_xxx" for master and "cps_xxx" for slave. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add support for the DB-88F8040 Armada 8k devel boardStefan Roese2016-12-05-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary files to support the Marvell Armada 8k devel board. Most board specfic files are shared with the Armada 7k boards under the name "armada-8k*". So only minimal changes are necessary to add this basic board support (except the DT files of course). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add slave CP area to the memory mapStefan Roese2016-12-05-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable access to the slave CP its memory needs to be added to the MMU memory map. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: armada-8k: Only configure xHCI power on DB-88F7040 boardStefan Roese2016-12-05-68/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses of_machine_is_compatible() to detect the board at runtime and only configured the I2C IO expander for the xHCI power / reset on the DB-88F7040 board. As this code will be used by other Armada-7k/8k ports, its necessary to use this runtime detection here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add Armada-80x0 dts/dtsi filesStefan Roese2016-12-05-0/+511
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the latest version of the DT files from the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Rename db-88f7040 files to armada-8kStefan Roese2016-12-05-15/+17
|/ | | | | | | | | | | | | | | | | This moves some of the Armada DB-88F7040 board specific files to a more generic name: armada-8k. This is in preparation for the Armada-8k support which will be added soon. And since both platforms share most devices, lets also share most source files to not duplicate the code here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-12-04-227/+276
|\
| * powerpc: mpc86xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig optionYork Sun2016-12-04-13/+6
| | | | | | | | | | | | Use Kconfig instead of defining this macro in header file. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc85xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig optionYork Sun2016-12-02-32/+48
| | | | | | | | | | | | Move the macro to Kconfig SYS_FSL_NUM_LAWS. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc86xx: Move CONFIG_FSL_LAW to KconfigYork Sun2016-12-02-5/+7
| | | | | | | | | | | | Clean up existing definitions and drop from white list. Signed-off-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-04 18:15:19 +0000