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* | arm: omap5: Add function to make an SMC call on cpu1Harinarayan Bhatta2016-12-03-0/+125
| | | | | | | | | | | | | | | | | | | | On DRA7xx platform, CPU Core 1 is not used in u-boot. However, in some cases it is need to make secure API calls from Core 1. This patch adds an assembly function to make a secure (SMC) call from CPU Core #1. Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | image: Add Trusted Execution Environment image typeAndrew F. Davis2016-12-03-0/+2
| | | | | | | | | | | | | | | | Add a new image type representing Trusted Execution Environment (TEE) image types. For example, an OP-TEE OS binary image. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | image: Add FIT image loadable section custom processingAndrew F. Davis2016-12-03-1/+66
| | | | | | | | | | | | | | | | | | | | | | To help automate the loading of custom image types we add the ability to define custom handlers for the loadable section types. When we find a compatible type while loading a "loadable" image from a FIT image we run its associated handlers to perform any additional steps needed for loading this image. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | davinci: omapl138_lcdk: add DT support for EMMC bootFabien Parent2016-12-03-1/+5
| | | | | | | | | | | | | | When booting from EMMC, load the DTB and pass it to the kernel. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: improve readability of boot commandFabien Parent2016-12-03-1/+18
| | | | | | | | | | | | | | | | Improve the readability of the boot command. This will help a later commit that adds DT support. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: add NAND SPL boot supportFabien Parent2016-12-03-28/+30
| | | | | | | | | | | | | | | | | | | | NAND SPL boot was missing. Add it. The README specific to omapl138-lcdk is also removed because its content does not apply anymore, i.e. the generated AIS image can be flashed directly to the NAND without using any external tool to create and bootable AIS image. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lck: remove obsolete defineFabien Parent2016-12-03-1/+0
| | | | | | | | | | | | | | | | | | NAND_MAX_CHIPS is not used anymore and has been replaced by CONFIG_SYS_MAX_NAND_DEVICE. There is no need to keep the former define. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: use correct name for CONFIG_SYS_NAND_MASK_ALEFabien Parent2016-12-03-2/+1
| | | | | | | | | | | | | | | | | | CONFIG_SYS_ALE_MASK is not used anywhere. It has probably been renamed to CONFIG_SYS_NAND_MASK_ALE. Rename it and remove the former from the config_whitelist.txt file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: use correct name for CONFIG_SYS_NAND_MASK_CLEFabien Parent2016-12-03-2/+1
| | | | | | | | | | | | | | | | | | CONFIG_SYS_CLE_MASK is not used anywhere. It has probably been renamed to CONFIG_SYS_NAND_MASK_CLE. Rename it and remove the former from the config_whitelist.txt file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: use correct define for 16 bit NAND chipsFabien Parent2016-12-03-2/+1
| | | | | | | | | | | | | | | | | | | | The omapl138_lcdk header defines CONFIG_SYS_NAND_BUSWIDTH_16_BIT while the correct name is CONFIG_SYS_NAND_BUSWIDTH_16BIT. While renaming the only occurrence of CONFIG_SYS_NAND_BUSWIDTH_16_BIT, let's also remove it from the config_whitelist.txt file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | NAND: davinci: add support for NAND chips with 16 bits busFabien Parent2016-12-03-0/+3
| | | | | | | | | | | | | | | | The OMAPL138-LCD board uses a NAND chip with a 16 bits bus. Add support into the davinci driver for 16 bit bus NAND chips. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: add u-boot sector for mmc/sd bootFabien Parent2016-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | Set the correct CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR value in order to be able to boot from MMC/SD. The SPL is stored at sector 0x75, while u-boot will follow at sector 0xb5. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: da850evm: fix empty boot method list in the SPLFabien Parent2016-12-03-0/+3
| | | | | | | | | | | | | | | | | | | | The list of available boot method is not part of the binary which prevent the SPL from booting u-boot or Linux. Add the missing .u_boot_list* sections to the binary to fix it. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: configure ddr2Fabien Parent2016-12-03-0/+42
| | | | | | | | | | | | | | | | The SPL is unable to load u-boot because the DDR2 is not configured. Configure the DDR2. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | davinci: omapl138_lcdk: configure pll0Fabien Parent2016-12-03-0/+1
| | | | | | | | | | | | | | | | The SPL is not able to boot properly because the PLL0 is not configured. Configure it. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: davinci: Move CONFIG_SYS_DA850_DDR_INIT to KconfigFabien Parent2016-12-03-5/+7
| | | | | | | | | | | | | | | | Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: davinci: Move CONFIG_SYS_DA850_PLL_INIT to KconfigFabien Parent2016-12-03-5/+7
| | | | | | | | | | | | | | | | Clean config headers by moving CONFIG_SYS_DA850_PLL_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XXNishanth Menon2016-12-03-17/+15
| | | | | | | | | | | | | | | | | | | | | | CONFIG_AM57XX is just an unnecessary macro that is redundant given So, remove the same instead of spreading through out the u-boot source code and getting in the way to maintain common code for DRA7x family. Acked-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | usb: xhci: Remove assumption of DWC instance based on DRA7 SoC typeNishanth Menon2016-12-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Both AM57xx and DRA7xx share the same set of base addresses for DWC controllers. The usage however differ with DWC2 instance used typically in AM57xx evms while DWC1 instances used in DRA7x platforms. Use TARGET_SOC config to differentiate so that CONFIG_AM57XX can be dropped. Eventually, this needs to be dt-fied. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: K2G: DDR3: Fix up priv ID for MPUNishanth Menon2016-12-03-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ECC enabled DDR, we use EDMA to reset all memory values to 0. For K2E/L/H/K the priv ID of 8 was indicative of ARM, but that is not the case for K2G, where it is 1. Unfortunately, ddr3 code had hard coded the privID and had missed identification previously. Fix the same, else unforeseen behavior can be expected in our reset of DDR contents to 0 for ECC enablement. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: AMx3xx: Make FIT boot as default boot on HS devicesLokesh Vutla2016-12-03-0/+14
| | | | | | | | | | | | | | | | Verification has to be done before booting any images on HS devices. So default the boot to FIT on HS devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: AM57xx: Make FIT boot as default boot on HS devicesLokesh Vutla2016-12-03-0/+8
| | | | | | | | | | | | | | | | Verification has to be done before booting any images on HS devices. So default the boot to FIT on HS devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Make FIT boot as default boot on HS devicesLokesh Vutla2016-12-03-0/+7
| | | | | | | | | | | | | | | | Verification has to be done before booting any images on HS devices. So default the boot to FIT on HS devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ti_armv7_common: env: Add support for loading FIT imagesLokesh Vutla2016-12-03-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FIT is a new image format which is a Tree like structure and gives more flexibility in handling of various images. Mainly used for unification of multiple images in a single blob and provide security information for each image. U-Boot already has support for loading such images, so adding the environment support to load FIT image on all TI platforms. Reviewed-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ti_armv7_common: env: Consolidate support for loading images from mmcLokesh Vutla2016-12-03-63/+27
| | | | | | | | | | | | | | | | | | | | Support for loading images from mmc is duplicated in all TI platforms. Add this information to DEFAULT_MMC_TI_ARGS so that it can be reused in all TI platforms. Reviewed-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | configs: am43x: hs: Modify SPL load address to fix UART boot issueMadan Srinivas2016-12-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An issue in the TI secure image generation tool causes the ROM to load the SPL at a different load address than what is specified by CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot. This causes the SPL to fail on secure devices during peripheral boot. The TI secure image generation tool has been fixed so that the SPL will always be loaded at 0x403018E0 by the ROM code for both peripheral and memory boot modes. am43x hs defconfig file have been updated to reflect this change. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | r2dplus: fixup CONFIG_SYS_TEXT_BASE to account arch/sh changesVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This change allows to reserve enough space at the end of board SDRAM to store two copies of U-Boot and malloc heap. Due to selection of the CONFIG_SYS_TEXT_BASE the second code/data copying is not avoided, first of all this may depend on a used toolchain, secondly at this point some level of volatility is wanted to do more platform changes and do not care about probably changed calculated in runtime relocation offset. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | sh: generate position independent code for all platformsVladimir Zapolskiy2016-12-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Finally add fpic compilation option to produce relocatable code. Note that this requires to define CONFIG_NEEDS_MANUAL_RELOC for all board files, also relocation support still has some limitations (e.g. a developer should care not to overwrite the executing code or memset() with zeroes not yet relocated data on malloc init etc.), which may be fixed while switching to PIE. Due to short investigation the architecture code is not ready for PIE linking, this will require some manipulations with .dyn* sections. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | sh: share the correct version of start.S among all cpusVladimir Zapolskiy2016-12-02-135/+9
| | | | | | | | | | | | | | | | | | | | | | It is easy to note that SH2/SH3/SH4 start.S code is practically the same with a minor difference for SH2 where a short data header is present. To avoid unwanted code duplication and to automatically convert SH2 and SH3 platforms to generic board support move fixed SH4 start.S into arch/sh/lib/start.S and share it among all platforms. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh4: fix start.S by calling board_init_f() after first code relocationVladimir Zapolskiy2016-12-02-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like on ARM platform keep the first code relocation from a U-boot image storage to RAM at CONFIG_SYS_TEXT_BASE, then pass execution to a generic board_init_f() with empty GD flags. If CONFIG_SYS_TEXT_BASE is equal to a calculated by board_init_f() relocation address there will be no more code and data copy, however it's worth to mention that the first copy happens even if $pc on _start is the same as CONFIG_SYS_TEXT_BASE, on practice this works without a problem. Also note that _sh_start is renamed back to _start to correct gd->mon_len calculation by setup_mon_len(), the opposite rename was done in pre-generic board commit 2024b968ee9 ("sh: Fix build in start.S"). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: add shared relocate_code() function and call board_init_r()Vladimir Zapolskiy2016-12-02-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Commits b61e90e6fd83 ("sh: Drop the arch-specific board init") and f41e6088eb1a ("sh: Fix build errors for generic board") left code and data relocation done in start.S, however further actual U-boot configuration is not started anymore. Practically SH boards with the code relocated into the expected position by start.S still can be booted, so the change adds this option and provides an option how to relocate code for board_init_r() execution. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: add common dram_init() function for all boardsVladimir Zapolskiy2016-12-02-230/+18
| | | | | | | | | | | | | | | | | | | | | | Generic board support assumes a different method of specifying DRAM size on board, also it can be shared among all boards, notably only sh7763rdp board has a custom legacy dram_init(), however the difference is only in printing some additional information, this feature can be removed. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: define CONFIG_DISPLAY_BOARDINFO to print board informationVladimir Zapolskiy2016-12-02-0/+27
| | | | | | | | | | | | | | | | | | All SH boards define a checkboard() function which outputs basic board information on boot, however generic board support requires to define CONFIG_DISPLAY_BOARDINFO to do that, so define it for the boards. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: remove undefined DEBUG preprocessor token from board config filesVladimir Zapolskiy2016-12-02-15/+0
| | | | | | | | | | | | | | | | | | | | By default this undef is a noop, moreover at this point when the platform support is broken is prevents debugging of U-boot by manual insertion of #define DEBUG into common files, so it makes sense to remove the option from all SH boards as a harmful one. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: add MEMORY command to a shared linker scriptVladimir Zapolskiy2016-12-02-16/+16
| | | | | | | | | | | | | | | | | | At the moment in runtime all defined sections are copied into or created in RAM, specify this explicitly to assert potential out of RAM placements of the sections. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: define entry point and reloc_dst inside a linker scriptVladimir Zapolskiy2016-12-02-6/+1
| | | | | | | | | | | | | | | | | | | | No functional change, concentrate linker script commands in one place for convenience. Entry point is set to CONFIG_SYS_TEXT_BASE by default on build, so this option can be omitted from being added to the linker script. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: place board lowlevel_init code in the beginning of .textVladimir Zapolskiy2016-12-02-19/+19
| | | | | | | | | | | | | | | | | | Reference lowlevel_init of all supported SH2A/SH3/SH4/SH4A boards from a shared linker script, the lowlevel_init function will be called by a relative address. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh4: use single u-boot linker script for all boardsVladimir Zapolskiy2016-12-02-253/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Three supported SH4/SH4A boards with the bootloader image stored on SPI flash have own flavour of a linker script, in turn they are equal among each other. The only difference is that the text from lowlevel_init.o is placed right after start.o, which makes sense. Note that .bss section is not marked as NOLOAD, because for about 10 years this is a default option of a GNU linker, either the attribute is found or not the resulting image file is the same. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | common: sh: add necessary define bits to board_fVladimir Zapolskiy2016-12-02-6/+9
| | | | | | | | | | | | | | | | | | | | Since a platform conversion to generic board support has not been accomplished some architecture specific bits are missing from board_f init sequence, the change adds a number of basic expected callbacks into early init sequence. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | r2dplus: select rtl8139 driver in defconfigVladimir Zapolskiy2016-12-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_RTL8139 was moved to a board defconfig by a commit 86e9dc86b1a2 ("net: Move CONFIG_RTL8139 to Kconfig"), however it was done incorrectly due to a missing CONFIG_NETDEVICES selection, thus virtually it was just a removal of the driver compilation. As an unlucky consequence the option was completely removed by a purge commit adad96e60d0e ("configs: Re-sync HUSH options"), restore the driver inclusion back. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | r2dplus: use P1 area space for text base and PCI system memoryVladimir Zapolskiy2016-12-02-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | While both options are acceptable use P1 area physical addresses instead of external memory space of text base and PCI system memory for unification purposes, all other supported superh boards have the same selection. This allows to easily ensure that CONFIG_SYS_TEXT_BASE is located within available DRAM. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh4: remove __io config options from r2dplus and r7780mp boardsVladimir Zapolskiy2016-12-02-12/+0
| | | | | | | | | | | | | | | | Defined __io is no-op for the SH architecture and it can be removed from board files without any functional change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pci: sh7751: map PCI memory space into SDRAMVladimir Zapolskiy2016-12-02-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | For ease of use and accounting a condition that on SH4 pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to unimplemented __iomem() conversion, this change fixes access to SDRAM memory by PCI devices. This change also generalizes PCI system memory configuration, which is taken from board specific defines rather than hardcoded in the PCI host driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | pci: sh7751: fix up PCI I/O space addressVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The change actually maps PCI I/O window to the same address on PCI bus as it is stated by a comment, before the change transfers to the PCI I/O space are failed due to misconfiguration of the most significant 14 bits of the PCI address in PCIIOBR (note that it is set to 0x0). Most probably the problem remained unnoticed, because communcation to all tested PCI devices is done over PCI memory space only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | sh4: cache: move exported cache manipulation functions into cache.cVladimir Zapolskiy2016-12-02-39/+36
| | | | | | | | | | | | | | | | | | No functional change, moving cache manipulation functions into cache.c allows to collect all of them in a single location and as a pleasant side effect cache_control() function can be unexported now. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh: cache: don't modify CCR from P1 areaVladimir Zapolskiy2016-12-02-5/+3
| | | | | | | | | | | | | | | | | | | | | | cache_wback_all() is a local function and it is called from cache_control() only, which is in turn jumps to P2 area. The change fixes an issue when cache_wback_all() returns from P2 to P1, however cache_control() continues to manipulate with CCR register, according to the User's Manual this is restricted. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | sh: cache use jump_to_P2() and back_to_P1() from asm/system.hVladimir Zapolskiy2016-12-02-37/+2
| | | | | | | | | | | | | | | | Both jump_to_P2() and back_to_P1() functions are found in asm/system.h header file and functionally they are the same, don't redefine them. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh3: remove unused cache.c file from being builtVladimir Zapolskiy2016-12-02-97/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The change is similar to commit 994b56616bae ("sh: delete an unused source file") for SH2, however here the removed cache.c file was built and included into an image as a dead code. If it is needed in future the contents can be reused from a similar arch/sh/cpu/sh4/cache.c file, which is in turn will be moved to a shared among all core flavours location at arch/sh/lib/cache.c. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh4: cache: correct flush_cache() to writeback and invalidateVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | | | | | | In common usecases flush_cache() assumes both cache invalidation and write-back to memory, instead of doing cache invalidation only with the wrapped 'ocbi' instruction pin flush_cache() to cache invalidation with memory write-back done by 'ocbp'. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sh4: cache: correct dcache flush to invalidate with write-backVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In common usecases flush_cache() assumes both cache invalidation and write-back to memory, thus in flush_dcache_range() implementation change SH4 cache write-back only instruction 'ocbwb' with cache purge instruction 'ocbp', according to the User's Manual there should be no performance penalty for that. Note that under circumstances only cache invalidation is expected from flush_cache() call, in these occasional cases the current version of flush_cache() works, which is a wrapper over invalidate_dcache_range() at the moment, this will be fixed in the following change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
generated by cgit v1.1 at 2024-11-09 22:13:11 +0000